501R18N120KP4E datasheet, PDF - EEWORLD Datasheet

501R18N120KP4E: DescriptionCeramic Capacitor, Ceramic, 500V, 10% +Tol, 10% -Tol, NP0, -/+30ppm/Cel TC, 0.000012uF, 1206,; CategoryPassive components capacitor; File Size534KB，4 Pages; ManufacturerJohanson Dielectrics; Environmental Compliance

Download Datasheet Parametric View All

501R18N120KP4E Overview

Ceramic Capacitor, Ceramic, 500V, 10% +Tol, 10% -Tol, NP0, -/+30ppm/Cel TC, 0.000012uF, 1206,

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	813700301
package instruction	, 1206
Reach Compliance Code	unknown
ECCN code	EAR99
capacitance	0.000012 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	1.78 mm
JESD-609 code	e4
length	3.18 mm
negative tolerance	10%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	SMT
method of packing	TR, Embossed, 7 Inch
positive tolerance	10%
Rated (DC) voltage (URdc)	500 V
Guideline	MIL-C-55681
series	HIGH VOLTAGE CHIP
size code	1206
Temperature characteristic code	NP0
Temperature Coefficient	30ppm/Cel ppm/°C
Terminal surface	Palladium/Silver (Pd/Ag)
width	1.58 mm

ALTERA device pin voltage: The voltage of device pins generally depends on VCCIO. So are the voltages of some specific configuration pins also referenced to VCCIO?...; eeleader FPGA/CPLD

I would like to ask: How do I measure the output of this simple optocoupler?: I want to ask how to measure the output of this MOCD optocoupler? I tried to use it, but failed. I want to ask you how to build a circuit to measure it? I want to talk about my method first: Due to th...; benny512 Analog electronics

The 4th volume of Mr. Yang's new book "New Concept Analog Circuits" is online! Hurry up if you need it~: [align=left][font=微软雅黑Light]Dangdangdang[/font]~[/align][align=left][font=微软雅黑Light]Everyone has been waiting for a long time. The fourth book in the "New Concept Analog Circuit" series, "Signal Proce...; 电路艺术 Analog electronics

FPGA Design and Application: FPGA Design and Application [local]2[/local] Welcome to download, it's free!...; eeleader FPGA/CPLD

Waiting online, problem with making LM7805 with proteus components: I can't succeed all the time. What does this problem mean? [img]http://pic.yupoo.com/wcycongying/78780934b84e/bnwved05.jpg[/img] [[i] This post was last edited by wcycongying on 2010-4-23 14:48[/i]]...; wcycongying PCB Design

FPGA Implementation of Digital Frequency Synthesizer: [b]Abstract: [/b]The principle of DDFS and the main features of ACEX 1K, an FPGA device of Altera, are introduced. The working principle, design ideas, circuit structure and simulation results of the ...; maker FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components