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DS1000M-75-IND

Description
SILICON DELAY LINE, TRUE OUTPUT, PDIP8, 0.300 INCH, DIP-8
Categorylogic    logic   
File Size67KB,6 Pages
ManufacturerMaxim
Websitehttps://www.maximintegrated.com/en.html
Download Datasheet Parametric View All

DS1000M-75-IND Overview

SILICON DELAY LINE, TRUE OUTPUT, PDIP8, 0.300 INCH, DIP-8

DS1000M-75-IND Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMaxim
Parts packaging codeDIP
package instructionDIP,
Contacts8
Reach Compliance Codeunknown
Is SamacsysN
seriesCMOS/TTL
Input frequency maximum value (fmax)8.33333 MHz
JESD-30 codeR-PDIP-T8
JESD-609 codee0
length9.375 mm
Logic integrated circuit typeSILICON DELAY LINE
Number of functions1
Number of taps/steps5
Number of terminals8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
programmable delay lineNO
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Total delay nominal (td)75 ns
width7.62 mm
Base Number Matches1
DS1000-IND
Industrial Temperature Range
5-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon time delay
5 taps equally spaced
Delays are stable and precise
Both leading and trailing edge accuracy
Delay tolerance
±5%
or
±2
ns, whichever is
greater (@25°C)
Delays characterized over -40°C to +85°C
temperature range (±2 ns or
±8%)
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Fast turn prototypes
IN
NC
NC
TAP 2
NC
TAP 4
GND
PIN ASSIGNMENT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
NC
TAP 1
TAP 4
NC
GND
TAP 3
NC
TAP 5
4
5
TAP 5
3
6
TAP 3
IN
TAP 2
1
2
8
7
V
CC
TAP 1
DS1000M-IND 8-PIN DIP
(300 MIL)
See Mech. Drawings Section
IN
TAP 2
TAP 4
GND
1
2
3
4
8
7
6
5
V
CC
TAP 1
TAP 3
TAP 5
DS1000-IND 14-PIN DIP
(300 MIL)
See Mech. Drawings Section
DS1000Z-IND 8-PIN SOIC
(150 MIL)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-TAP 5
V
CC
GND
NC
IN
- TAP Output Number
- +5 Volts
- Ground
- No Connection
- Input
DESCRIPTION
The DS1000-IND series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns.
These devices are offered in standard 8- and 14-pin DIPs that are pin-compatible with hybrid delay lines.
Alternatively, 8-pin SOICs are available to save PC board area. Low cost and superior reliability over
hybrid technology is achieved by the combination of a 100% silicon delay line and industry standard DIP
and SOIC packaging. In order to maintain complete pin compatibility, DIP packages are available with
hybrid lead configurations. The DS1000-IND series delay lines provide a nominal accuracy of
±5%
or
±2
ns, whichever is greater. The DS1000-IND 5-Tap Silicon Delay Line reproduces the input logic state
at the output after a fixed delay as specified by the extension of the part number after the dash. The
DS1000-IND is designed to reproduce both leading and trailing edges with equal precision. Each tap is
capable of driving up to ten 74LS loads.
Dallas Semiconductor can customize standard products to meet special needs. For special requests and
rapid delivery, call (972) 371-4348.
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