530MA1251M00BGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 530MA1251M00BGR

530MA1251M00BGR: DescriptionLVPECL Output Clock Oscillator, 1251MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size268KB，15 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

530MA1251M00BGR Overview

LVPECL Output Clock Oscillator, 1251MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530MA1251M00BGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
Reach Compliance Code	unknown
Is Samacsys	N
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	530
Installation features	SURFACE MOUNT
Nominal operating frequency	1251 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.0 7/06

Si530/531

Recommended Resources

AD574A Unipolar and Bipolar Input Circuitb

High output voltage amplifier circuit

BA8105 (electric fan) infrared remote control receiving control circuit

Steam iron automatic protection circuit

ansco camera flash circuit

Topology of single-ended primary inductor converter consisting of BQ24007

Let's DIY an FPGA development board, here is the circuit diagram, welcome to check for errors: I haven't updated you all for a long time since I asked [url=https://bbs.eeworld.com.cn/thread-84156-1-1.html] us to DIY an FPGA development board. Sign up~~~[/url]. The attachment is the circuit diag...; jyl FPGA/CPLD

Breaking news: Chunyang is on the news!: [i=s]This post was last edited by wangfuchong on 2014-1-29 14:05[/i] Breaking News! Shenzhen X News: On the night of January 28, Shenzhen XX Police Station received a call from a woman, claiming that ...; wangfuchong Talking

What exactly is the so-called oscillator on the antenna? Can you explain it in a vivid way? ? ?: What exactly is the so-called vibrator on the antenna? Can you explain it in a vivid way? Or post a picture to show the real thing (I don't know whether the vibrator is a real thing or a more vivid na...; debugme RF/Wirelessly

Is there any simulation software like this?: Is there any such simulation software? I just learned AVR microcontrollers and I used a learning board. I feel that the functions of the learning board are very limited. I found that the circuit simul...; dadat Embedded System

Generate random 0,1 signal: The original program was for STM32F103ZE, I changed it to STM32F103C8T6, and it compiled fine, but there was no output, why? I want to generate a random 0,1 signal, is there any way to do it?...; swyewuk stm32/stm8

Problems using Saber to simulate SPWM driving H-bridge via 2110: When using Saber simulation, directly driving the H-bridge with PWM signal can output waveform, as shown in the figure. Whenadding IR2110 isolation driver when PWM signal is generated and H-bridge is ...; chen_x Power technology

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components