A29L800A Series
1M X 8 Bit / 512K X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Features
Single power supply operation
- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
Access times:
-
70/90 (max.)
Current:
- 9 mA typical active read current
- 20 mA typical program/erase current
-
200 nA typical CMOS standby
-
200 nA Automatic Sleep Mode current
Flexible sector architecture
-
16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
-
8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that sector
Extended operating temperature range: -40°C ~ +85°C for -
U series; -25°C ~ +85°C for – I series
Unlock Bypass Program Command
- Reduces overall programming time when issuing multiple
program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
-
Reliable operation for the life of the system
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
-
Superior inadvertent write protection
Data
Polling and toggle bits
-
Provides a software method of detecting completion of
program or erase operations
Ready /
BUSY
pin (RY /
BY
)
- Provides a hardware method of detecting completion of
program or erase operations (not available on 44-pin
SOP)
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array data
Package options
-
44-pin SOP or 48-pin TSOP (I) or 48-ball TFBGA
-
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A29L800A is an 8Mbit, 3.0 volt-only Flash memory
organized as 1,048,576 bytes of 8 bits or 524,288 words of 16
bits each. The 8 bits of data appear on I/O
0
- I/O
7
; the 16 bits of
data appear on I/O
0
~I/O
15
. The A29L800A is offered in 48-ball
TFBGA, 44-pin SOP and 48-Pin TSOP packages. This device
is designed to be programmed in-system with the standard
system 3.0 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However, the
A29L800A can also be programmed in standard EPROM
programmers.
The A29L800A has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O
6
toggle bit, the
A29L800A has a second toggle bit, I/O
2
, to indicate whether
the addressed sector is being selected for erase. The
A29L800A also offers the ability to program in the Erase
Suspend mode. The standard A29L800A offers access times
of 70 and 90ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention the
device has separate chip enable (
CE
), write enable (
WE
)
and output enable (
OE
) controls.
The device requires only a single 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L800A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve
as input to an internal state-machine that controls the erase
and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation. During erase, the device
automatically times the erase pulse widths and verifies proper
erase margin. The Unlock Bypass mode facilitates faster
programming times by requiring only two write cycles to
program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY /
BY
pin, or by
reading the I/O
7
(
Data
Polling) and I/O
6
(toggle) status bits.
(April, 2009, Version 1.6)
1
AMIC Technology, Corp.
A29L800A Series
After a program or erase cycle has been completed, the device
is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29L800A is fully erased when shipped
from the factory.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware
RESET
pin terminates any operation in
progress and resets the internal state machine to reading
array data. The
RESET
pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When addresses
have been stable for a specified amount of time, the device
enters the automatic sleep mode. The system can also place
the device into the standby mode. Power consumption is
greatly reduced in both these modes.
Pin Configurations
SOP
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
I/O
0
I/O
8
I/O
1
I/O
9
I/O
2
I/O
10
I/O
3
I/O
11
1
2
3
4
5
6
7
44
43
42
41
40
39
38
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
TSOP (I)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A29L800A
8
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A29L800AV
(April, 2009, Version 1.6)
2
AMIC Technology, Corp.
NXP MCU
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