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P4C116L-35DM

Description
Standard SRAM, 2KX8, 35ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24
Categorystorage    storage   
File Size1MB,15 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C116L-35DM Overview

Standard SRAM, 2KX8, 35ns, CMOS, CDIP24, 0.300 INCH, CERAMIC, DIP-24

P4C116L-35DM Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeDIP
package instructionDIP, DIP24,.3
Contacts24
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time35 ns
I/O typeCOMMON
JESD-30 codeR-CDIP-T24
JESD-609 codee0
length31.75 mm
memory density16384 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals24
word count2048 words
character code2000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize2KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum standby current0.0006 A
Minimum standby current2 V
Maximum slew rate0.14 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
P4C116/P4C116L
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35 ns (Military)
Low Power Operation
Output Enable Control Function
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Produced with PACE II Technology
TM
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOIC, SOJ
– 24-Pin 600 mil DIP
– 24-Pin Solder Seal Flat Pack
– 24-Pin Rectangular LCC (300 x 400 mils)
– 28-Pin Square LCC (450 x 450 mils)
– 32-Pin Rectangular LCC (450 x 550 mils)
– 40-Pin Square LCC (480 x 480 mils)
DESCRIPTIOn
The P4C116/P4C116L are 16,384-bit ultra high-speed
static RAMs organized as 2K x 8. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
Current drain is typically 10 µA from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C116 is available in 24-pin 300 and 600 mil DIP,
SOJ and SOIC packages, a solder seal flatpack and 4
different LCC packages (24, 28, 32, and 40 pin).
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (C4, C12, D4, P4), SOJ (J4), SOIC (S4)
SOLDER SEAL FLAT PACK (FS-1) SIMILAR
LCC configurations at end of datasheet
Document #
SRAM110
REV C
Revised May 2009
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