531KB466M000DGR datasheet, PDF

Datasheet> All Categories > Passive components> oscillator> 531KB466M000DGR

531KB466M000DGR: DescriptionCMOS/TTL Output Clock Oscillator, 466MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531KB466M000DGR Overview

CMOS/TTL Output Clock Oscillator, 466MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531KB466M000DGR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	466 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

ADT70 pin function diagram

One of multiple sets of high-power colored light chain circuits that flash in turn a

Use three switches to control a light circuit

Astable flip-flop with starter

T6668 is used for bus stop announcer

80V effective value analog switch circuit diagram

DSPF28335 Study Notes: [i=s]This post was last edited by Aguilera on 2018-12-24 20:41[/i] [size=4]1. GPIO[/size] [size=4]GPxMUX (function selection register),[/size] [size=4] GPxMUX.bit=0 is configured as I/O function. GPxM...; Aguilera DSP and ARM Processors

String line splitting problem: I have a string like this. Each line ends with a carriage return, and the hexadecimal is OD OA. I want to split the following string into lines, and execute it under WINCE. I would like to ask an expe...; oscar19841024 Embedded System

Voltage problem between the pins connecting two components in PCB: During the debugging of the PCB board, a pin of component A is connected to a pin of component B, but the voltage between the two pins is not 0V, but 0.5V. Why is this? (Because the circuit in the fol...; 静静地期待 PCB Design

A Practical Guide to High-Frequency and High-Speed PCB Design (Part 1): 1. After the PCB design is completed, how to choose the PCB material? The selection of PCB material must strike a balance between meeting the design requirements and mass production and cost. The desi...; 高速PCB设计 PCB Design

Microcontroller Tutorial - Timer: Microcontroller Tutorial...; liuliu408 MCU

Looking for a 16*16 dot matrix screen circuit diagram and source program: [size=5]I need to use 4 8*8 dot matrices[/size][size=6][color=#ff0000][b] cascade[/b][/color][/size][size=5] to form a 16*16 dot matrix. Please provide the schematic diagram and source code. [/size]...; lq18134413428 Electronics Design Contest

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components