FemtoClock
TM
Crystal-To-3.3V, 2.5V
LVPECL Frequency Synthesizer
ICS843002I
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS843002I is a 2 output LVPECL synthesizer
optimized to generate Fibre Channel reference
HiPerClockS™
clock frequencies and is a member of the
HiPerClockS™ family of high performance clock
solutions from IDT. Using a 26.5625MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz, and
53.125MHz. The ICS843002I uses IDT’s FemtoClock
TM
low
phase noise VCO technology and can achieve 1ps or lower
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS843002I is packaged in a small 20-pin
TSSOP package.
F
EATURES
• Two 3.3V or 2.5V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @212.5MHz (2.55MHz - 20MHz):
0.50ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
Frequency
26.5625
26.5625
26.5625
26.5625
23.4375
Inputs
M Divider
F_SEL1 F_SEL0
Value
0
0
24
0
1
1
0
1
0
1
0
24
24
24
24
N Divider
Value
3
4
6
12
3
M/N
Divider Value
8
6
4
2
8
Output
Frequency
(MHz)
212.5
159.375
106.25
53.125
187.5
P
IN
A
SSIGNMENT
nc
V
CCO
Q0
nQ0
MR
nPLL_SEL
nc
V
CCA
F_SEL0
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CCO
Q1
nQ1
V
EE
V
CC
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
B
LOCK
D
IAGRAM
F_SEL[1:0]
Pulldown
nPLL_SEL
Pulldown
F_SEL[1:0]
2
ICS843002I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
Q0
00
01
10
11
÷3
÷4
÷6
÷12
nQ0
REF_CLK
Pulldown
1
1
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL
Pulldown
0
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
Q1
nQ1
0
M = 24 (fixed)
MR
Pulldown
ICS843002AGI REVISION A SEPTEMBER 11, 2009
1
©2009
Integrated Device Technology, Inc.
ICS843002I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 7
2, 20
3, 4
5
Name
nc
V
CCO
Q0, nQ0
MR
Type
Unused
Power
Ouput
Input
Description
No connect.
Output supply pins.
Differential output pair. LVPECL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing
the true outputs Qx to go low and the inver ted outputs nQx to go high. When logic
Pulldown
LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface
levels.
Determines whether synthesizer is in PLL or bypass mode.
Pulldown
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between crystal or REF_CLK inputs as the the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL
interface levels.
Negative supply pins.
Differential output pair. LVPECL interface levels.
6
8
9, 11
10, 16
12, 13
14
15
17
18, 19
nPLL_SEL
V
CCA
F_SEL0,
F_SEL1
V
CC
XTAL_OUT,
XTAL_IN
REF_CLK
nXTAL_SEL
V
EE
nQ1, Q1
Input
Power
Input
Power
Input
Input
Input
Power
Output
NOTE:
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
ICS843002AGI REVISION A SEPTEMBER 11, 2009
2
©2009
Integrated Device Technology, Inc.
ICS843002I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
73.2°C/W (0 lfpm)
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.97
2.97
2.97
Typical
3.3
3.3
3.3
Maximum
3.63
3.63
3.63
130
13
Units
V
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
2.625
2.625
115
12
Units
V
V
V
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.63V or 2.625V
V
CC
= 3.63V or 2.625V,
V
IN
= 0V
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
I
IL
-150
µA
ICS843002AGI REVISION A SEPTEMBER 11, 2009
3
©2009
Integrated Device Technology, Inc.
ICS843002I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
3D. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
23.33
Test Conditions
Minimum
Typical
Fundamental
26.5625
28.33
50
7
1
MHz
Ω
pF
mW
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] =11
Minimum
186.67
140
93.33
46.67
0.50
0.54
0.68
0.70
350
650
Typical
Maximum
226.67
170
113.33
56.67
30
212.5MHz, (2.55MHz - 20MHz)
159.375MHz, (1.875MHz - 20MHz)
106.25MHz, (637kHz - 5MHz)
53.125MHz, (637kHz - 5MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
t
sk(o)
Output Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
t
jit(Ø)
F_SEL[1:0]
≠
00
49
51
%
F_SEL[1:0] = 00
43
57
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using cr ystal input.
ICS843002AGI REVISION A SEPTEMBER 11, 2009
4
©2009
Integrated Device Technology, Inc.
ICS843002I Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] =11
Minimum
186.67
140
93.33
46.67
0.50
0.55
0.75
0.76
350
650
Typical
Maximum
226.67
170
113.33
56.67
30
212.5MHz, (2.55MHz - 20MHz)
159.375MHz, (1.875MHz - 20MHz)
106.25MHz, (637kHz - 5MHz)
53.125MHz, (637kHz - 5MHz)
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
t
sk(o)
Output Skew; NOTE 1, 2
RMS Phase Jitter (Random);
NOTE 3
t
jit(Ø)
F_SEL[1:0]
≠
00
49
51
%
F_SEL[1:0] = 00
43
57
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured using cr ystal input.
ICS843002AGI REVISION A SEPTEMBER 11, 2009
5
©2009
Integrated Device Technology, Inc.
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