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TAS5733L
SLASE77A – MARCH 2016 – REVISED MARCH 2016
TAS5733L - Digital Input Audio Power Amplifier with EQ and 3-Band AGL
1 Features
1
2 Applications
•
•
LCD TV, LED TV
Low-Cost Audio Equipment
•
•
•
Audio Input/Output
– One-Stereo Serial Audio Input
– Supports 44.1-kHz and 48-kHz Sample Rates
(LJ/RJ/I²S)
– Supports 3-Wire I²S Mode (no MCLK required)
– Automatic Audio Port Rate Detection
– Supports BTL and PBTL Configuration
– P
OUT
= 10 W @ 10% THD+N
– PVDD = 12 V, 8
Ω,
1 kHz
Audio/PWM Processing
– Independent Channel Volume Controls With
Gain of 24 dB to Mute in 0.125-dB Steps
– Programmable Three-Band Automatic Gain
Limiting (AGL)
– 20 Programmable Biquads for Speaker EQ
and Other Audio-Processing Features
General Features
– 104-dB SNR, A-Weighted, Referenced to Full
Scale (0 dB)
– I²C Serial Control Interface w/ two Addresses
– Thermal, Short-Circuit, and Undervoltage
Protection
– Up to 90% Efficient
– AD, BD, and Ternary Modulation
– PWM Level Meter
Power vs PVDD
30
3 Description
The TAS5733L device is an efficient, digital-input
audio amplifier for driving stereo speakers configured
as a bridge tied load (BTL). In parallel bridge tied
load (PBTL) in can produce higher power by driving
the parallel outputs into a single lower impedance
load. One serial data input allows processing of up to
two discrete audio channels and seamless integration
to most digital audio processors and MPEG
decoders. The device accepts a wide range of input
data and data rates. A fully programmable data path
routes these channels to the internal speaker drivers.
The TAS5733L device is a slave-only device
receiving all clocks from external sources. The
TAS5733L device operates with a PWM carrier
between a 384-kHz switching rate and a 288-kHz
switching rate, depending on the input sample rate.
Oversampling combined with a fourth-order noise
shaper provides a flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
Device Information
(1)
PART NUMBER
TAS5733L
PACKAGE
HTSSOP (48)
BODY SIZE (NOM)
12.50 mm × 6.10 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
DVDD
AVDD
PVDD
Power-On Reset
(POR)
MCLK Monitoring
and Watchdog
RL = 4
25
RL = 8
Internal Regulation and Power Distribution
Internal Voltage Supplies
20
Output Power (W)
Digital to PWM
Converter
(DPC)
Open Loop Stereo
Stereo PWM Amplifier
Sensing & Protection
Temperature
Short Circuits
PVDD Voltage
Output Current
Fault Notification
MCLK
LRCK
Serial Audio Port
(SAP)
Sample Rate
Auto-Detect
PLL
Digital Audio
Processor
(DAP)
Sample Rate
Converter
(SRC)
2 Ch. PWM
Modulator
Noise Shaping
Click & Pop
Suppression
AMP_OUT_A
AMP_OUT_B
15
SCLK
SDIN
AMP_OUT_C
AMP_OUT_D
10
5
Internal Register/State Machine Interface
0
8
9
10
11
12
13
14
15
I²C Control Port
PVDD (V)
SCL
SDA
DR_SD
PDN
RST
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5733L
SLASE77A – MARCH 2016 – REVISED MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
1
1
1
2
3
5
8
Absolute Maximum Ratings ......................................
5
ESD Ratings ............................................................
5
Recommended Operating Conditions.......................
5
Thermal Characteristics ............................................
6
Electrical Characteristics...........................................
6
Speaker Amplifier Characteristics.............................
7
Protection Characteristics .........................................
7
Master Clock Characteristics ....................................
7
I²C Interface Timing Requirements ...........................
8
Serial Audio Port Timing Requirements..................
8
Typical Characteristics - Stereo BTL Mode ..........
11
Typical Characteristics - Mono PBTL Mode .........
13
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Overview .................................................................
Functional Block Diagram .......................................
Audio Signal Processing Overview .........................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
15
15
16
17
19
20
31
Application and Implementation
........................
49
8.1 Application Information............................................
49
8.2 Typical Applications ...............................................
50
9 Power Supply Recommendations......................
55
10 Layout...................................................................
56
10.1 Layout Guidelines .................................................
56
10.2 Layout Example ....................................................
57
11 Device and Documentation Support
.................
59
11.1 Trademarks ...........................................................
59
11.2 Electrostatic Discharge Caution ............................
59
11.3 Glossary ................................................................
59
7
Detailed Description
............................................
15
12 Mechanical, Packaging, and Orderable
Information
...........................................................
60
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2016) to Revision A
•
Page
Moved from Product Preview to Production Data release. ...................................................................................................
1
2
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Copyright © 2016, Texas Instruments Incorporated
TAS5733L
www.ti.com
SLASE77A – MARCH 2016 – REVISED MARCH 2016
5 Pin Configuration and Functions
DCA Package
48-Pin HTSSOP With PowerPAD™
Top View
BSTRP _B
AMP_OUT _B
AMP_OUT _B
PGND
PGND
AMP_OUT _A
PVDD
PVDD
BSTRP _A
SSTIMER
PBTL
NC
NC
PLL _GND
PLL _FLTM
PLL _FLTP
AVDD _REF
AVDD
ADR / FAULT
MCLK
OSC_RES
OSC _GND
DVDD_REG
PDN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BSTRP _C
AMP_OUT _C
AMP_OUT _C
PGND
PGND
AMP_OUT _D
PVDD
PVDD
BSTRP _D
GVDD _REG
AVDD_ REG
NC
NC
AGND
DGND
DVDD
TEST
RST
NC
SCL
SDA
SDIN
SCLK
LRCLK
PowerPAD
TM
Pin Functions
PIN
NAME
ADR/FAULT
AGND
AMP_OUT_A
AMP_OUT_B
AMP_OUT_C
AMP_OUT_D
AVDD
AVDD_REF
AVDD_REG
BSTRP_A
BSTRP_B
BSTRP_C
BSTRP_D
DGND
DVDD
DVDD_REG
NO.
19
35
6
2
3
46
47
43
18
17
38
9
1
48
40
34
33
23
P
P
P
Ground reference for digital circuitry (NOTE: This terminal should be connected to the
system ground)
Power supply for the internal digital circuitry
Voltage regulator derived from DVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
Voltage regulator derived from PVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
Word select clock for the digital signal that is active on the input data line of the serial
port
P
Connection points to for the bootstrap capacitors, which are used to create a power
supply for the gate drive for the high-side device
P
P
P
Power supply for internal analog circuitry
Internal power supply (NOTE: This terminal is provided as a connection point for filtering
capacitors for this supply and must not be used to power any external circuitry)
Voltage regulator derived from AVDD supply (NOTE: This terminal is provided as a
connection point for filtering capacitors for this supply and must not be used to power
any external circuitry)
AO
Speaker amplifier outputs
TYPE
(1)
DESCRIPTION
Dual function terminal which sets the LSB of the I²C Address to 0 if pulled to GND, 1 if
pulled to AVDD. Also, if configured to be a fault output by the methods described in the
Fault Indication
section, this terminal will be pulled low when an internal fault occurs.
Ground reference for analog circuitry (NOTE: This terminal should be connected to the
system ground)
DI/DO
P
GVDD_REG
LRCLK
(1)
39
25
P
DI
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
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3
Copyright © 2016, Texas Instruments Incorporated
TAS5733L
SLASE77A – MARCH 2016 – REVISED MARCH 2016
www.ti.com
Pin Functions (continued)
PIN
NAME
MCLK
NO.
20
12
13
NC
(2)
30
36
37
OSC_GND
OSC_RES
PBTL
PDN
22
21
11
24
4
PGND
5
44
45
PLL_FLTM
PLL_FLTP
PLL_GND
15
16
14
7
PVDD
8
41
42
RST
SCL
SCLK
SDA
SDIN
SSTIMER
TEST
31
29
26
28
27
10
32
DI
DI
DI
DI/DO
DI
AO
—
Places the devices in reset when pulled low
I²C serial control port clock
Bit clock for the digital signal that is active on the input data line of the serial data port
I²C serial control port data
Data line to the serial data port
Connection point for the capacitor that is used by the ramp timing circuit, as described in
the
SSTIMER Pin Functionality
section
Used by TI for testing during device production (NOTE: This terminal should be
connected to system ground)
Exposed metal pad on the underside of the device, which serves as an electrical
connection point for ground as well as a heat conduction path from the device into the
board (NOTE: This terminal should be connected to ground through a land pattern
defined in the
Mechanical Data
section)
P
Power supply for internal power circuitry
AO
AO
P
Negative connection point for the PLL loop filter components
Positive connection point for the PLL loop filter components
Ground reference for PLL circuitry (NOTE: This terminal should be connected to the
system ground)
—
Ground reference for power device circuitry (NOTE: This terminal should be connected
to the system ground)
P
AO
DI
DI
Ground reference for oscillator circuitry (NOTE: These terminals should be connected to
the system ground)
Connection point for precision resistor used by internal oscillator circuit. Details for this
resistor are shown in the
Typical Applications
section
Places the power stage in BTL mode when pulled low, or in PBTL mode when pulled
high
Places the device in power down when pulled low
P
Not connected inside the device (all "no connect" terminals should be connected to
system ground)
TYPE
(1)
DI
DESCRIPTION
Master clock used for internal clock tree and sub-circuit/state machine clocking
PowerPAD
—
P
(2)
Although these pins are not connected internally, optimum thermal performance is realized when these pins are connected to the ground
plane. Doing so allows copper on the PCB to fill up to and including these pins, providing a path for heat to conduct away from the
device and into the surrounding PCB area.
4
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TAS5733L
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SLASE77A – MARCH 2016 – REVISED MARCH 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
Supply voltage
DVDD, AVDD
PVDD
3.3-V digital input
Input voltage
5-V tolerant
(2)
UNIT
V
–0.3 to 3.6
–0.3 to 20
–0.5 to DVDD + 0.5
–0.5 to DVDD + 2.5
(3)
–0.5 to AVDD + 2.5
22
(4)
29
(4)
(3)
digital input (except MCLK)
V
V
V
°C
°C
5-V tolerant MCLK input
AMP_OUT_x to GND
BSTRP_x to GND
Operating free-air temperature
Storage temperature range, T
stg
(1)
(2)
(3)
(4)
0 to 85
–40 to 125
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RST, SCLK, LRCK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6 V.
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
V
(ESD)
(1)
(2)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-
C101
(2)
±4000
±1500
V
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
DVDD, AVDD
PVDD
V
IH
V
IL
T
A
T
J
R
L
R
L
L
O
(1)
(2)
(2)
NOM
3.3
MAX
3.6
16.5
(1)
(2)
UNIT
V
V
V
Digital, analog supply voltage
Output power devices supply voltage
High-level input voltage
Low-level input voltage
Operating ambient temperature range
Operating junction temperature range
Load impedance
Load impedance in PBTL
Output-filter inductance
Minimum output inductance under
short-circuit condition
5-V tolerant
5-V tolerant
3
8
2
0.8
0
0
4
2
10
8
85
125
V
°C
°C
Ω
Ω
μH
For operation at PVDD levels greater than 14.5 V, the modulation limit must be set to 96.1% or lower via the control port register 0x10.
16.5 V is the maximum recommended voltage for continuous operation of the TAS5733L device. Testing and characterization of the
device is performed up to and including 16.5 V to ensure “in system” design margin. However, continuous operation at these levels is
not recommended. Operation above the maximum recommended voltage may result in reduced performance, errant operation, and
reduction in device reliability.
Copyright © 2016, Texas Instruments Incorporated
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