DSC510-054221KE1T datasheet, PDF

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DSC510-054221KE1T: DescriptionOTHER CLOCK GENERATOR; CategoryThe embedded processor and controller Microcontrollers and processors; File Size684KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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DSC510-054221KE1T Overview

OTHER CLOCK GENERATOR

DSC510-054221KE1T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
package instruction	HVQCCN,
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	ELIMINATED THE EXT QUARTZ CRYSTAL AND USED MEMS CLOCK GENERATORS AS EXT CLOCK
JESD-30 code	R-XQCC-N20
length	5 mm
Humidity sensitivity level	1
Number of terminals	20
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Maximum output clock frequency	460 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Filter level	AEC-Q100
Maximum seat height	0.9 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	2.25 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	3.2 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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DSC510-05

Crystal-less™ Four Output LAN Clock Generator

General Description

The DSC510-05 is a Crystal-less™, four

output clock generator that implements

Discera’s

proven

PureSilicon™

MEMS

technology.

The devices implements

proven silicon MEMS technology to provide

excellent jitter and stability over a wide

range of supply voltages and temperatures.

By eliminating the external quartz crystal,

MEMS

clock

generators

significantly

enhance reliability and accelerate product

development, while meeting stringent clock

performance criteria for a variety of

communications, storage, and networking

applications.

DSC510-05 has an Output Enable / Disable

feature allowing it to disable all outputs

when OE1 and OE2 are low. Each output

enable pin controls one of the two banks of

synchronous clocks. See the OE function

table 1 for more detail.

The device is

available in a 20 pin QFN. Additional output

formats are in any combination of LVPECL,

LVDS, LVCMOS and HCSL.

Features



Four 25MHz LVPECL Clocks



Available Output Formats:

HCSL, LVPECL, LVCMOS, or LVDS

Mixed Outputs: LVPECL/HCSL/LVDS/CMOS

Ext. Industrial: -40° to 105° C

Industrial: -40° to 85° C

Ext. commercial: -20° to 70° C



Wide Temperature Range



Supply Range of 2.25 to 3.6 V



Low Power Consumption

30% lower than competing devices

Qualified to MIL-STD-883

20 QFN



Excellent Shock & Vibration Immunity



Available Footprints:



Lead Free & RoHS Compliant



Short Lead Time: 2 Weeks



AEC-Q100 Automotive Qualified



Block Diagram

Applications



Communications/Networking

Ethernet/ LAN PHY

1G, 10GBASE-T/KR/LR/SR, and FcoE

Routers and Switches

Gateways, VoIP, Wireless AP’s

Passive Optical Networks

Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are

25MHz clocks for LAN applications. For other

frequencies, please contact the factory.

_____________________________________________________________________________________________________________________________ _________________

DSC510-05

Page 1

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