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74HC4020D,652

Description
74HC4020; 74HCT4020 - 14-stage binary ripple counter SOP 16-Pin
Categorylogic    logic   
File Size282KB,17 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

74HC4020D,652 Overview

74HC4020; 74HCT4020 - 14-stage binary ripple counter SOP 16-Pin

74HC4020D,652 Parametric

Parameter NameAttribute value
Brand NameNexperia
Is it Rohs certified?conform to
MakerNexperia
Parts packaging codeSOP
package instruction3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16
Contacts16
Manufacturer packaging codeSOT109-1
Reach Compliance Codecompliant
Samacsys Confidence2
Samacsys StatusReleased
Samacsys PartID734210
Samacsys Pin Count16
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategorySmall Outline Packages
Samacsys Footprint NameSO16
Samacsys Released Date2019-11-12 07:41:52
Is SamacsysN
Other featuresOUTPUTS FROM 12 STAGES AVAILABLE
Counting directionUP
seriesHC/UH
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length9.9 mm
Load/preset inputYES
Logic integrated circuit typeBINARY COUNTER
Operating modeASYNCHRONOUS
Humidity sensitivity level1
Number of digits14
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)42 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typeNEGATIVE EDGE
width3.9 mm
minfmax20 MHz
Base Number Matches1
74HC4020; 74HCT4020
14-stage binary ripple counter
Rev. 7 — 18 June 2020
Product data sheet
1. General description
The 74HC4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an
overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3
to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all
counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a
static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors
to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
Input levels:
For 74HC4020: CMOS level
For 74HCT4020: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters

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