CY62128DV30L-55SI datasheet, PDF

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CY62128DV30L-55SI: Description1-Mb (128K x 8) Static RAM; File Size579KB，11 Pages; ManufacturerCypress Semiconductor

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CY62128DV30L-55SI Overview

1-Mb (128K x 8) Static RAM

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CY62128DV30

1-Mb (128K x 8) Static RAM

Features

• Very high speed: 55 and 70 ns

• Wide voltage range: 2.2V to 3.6V

• Pin compatible with CY62128V

• Ultra-low active power

— Typical active current: 0.85 mA @ f = 1 MHz

— Typical active current: 5 mA @ f = f

MAX

• Ultra-low standby power

• Easy memory expansion with CE

, CE

, and OE

features

• Automatic power-down when deselected

• Available in Pb-free and non Pb-free 32-lead SOIC,

32-lead TSOP and 32-lead Small TSOP, non Pb-free

32-lead Reverse TSOP packages

also has an automatic power-down feature that significantly

reduces power consumption by 90% when addresses are not

toggling. The device can be put into standby mode reducing

power consumption by more than 99% when deselected Chip

Enable 1 (CE

) HIGH or Chip Enable 2 (CE

) LOW. The

input/output pins (I/O

through I/O

) are placed in a

high-impedance state when: deselected Chip Enable 1 (CE

)

HIGH or Chip Enable 2 (CE

) LOW, outputs are disabled (OE

HIGH), or during a write operation (Chip Enable 1 (CE

) LOW

and Chip Enable 2 (CE

) HIGH and Write Enable (WE) LOW).

Writing to the device is accomplished by taking Chip Enable 1

(CE

) LOW with Chip Enable 2 (CE

) HIGH and Write Enable

(WE) LOW. Data on the eight I/O pins is then written into the

location specified on the Address pin (A

through A

Reading from the device is accomplished by taking Chip

Enable 1 (CE

) LOW with Chip Enable 2 (CE

) HIGH and

Output Enable (OE) LOW while forcing the Write Enable (WE)

HIGH. Under these conditions, the contents of the memory

location specified by the address pins will appear on the I/O

pins.

The eight input/output pins (I/O

through I/O

) are placed in a

high-impedance state when the device is deselected (CE

HIGH or CE

LOW), the outputs are disabled (OE HIGH) or

during a write operation (CE

LOW, CE

HIGH), and WE

LOW).

Functional Description

[1]

The CY62128DV30 is a high-performance CMOS static RAM

organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL

) in

portable applications such as cellular telephones. The device

Logic Block Diagram

Data in Drivers

A10

A11

ROW DECODER

I/O0

I/O1

SENSE AMPS

I/O2

I/O3

I/O4

I/O5

128K x 8

ARRAY

COLUMN

DECODER

Power-

down

I/O6

I/O7

A 12

A 13

A 14

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

A 15

A 16

Cypress Semiconductor Corporation

Document #: 38-05231 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised June 19, 2006

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