When MID or HIGH, disables Phase-locked Loop (PLL)
[3]
. REF goes to
outputs of Bank 1 and Bank 2. REF also goes to outputs of Bank 3 and Bank
4 through output dividers K and M. Set LOW for normal operation.
Synchronous Output Enable.
When HIGH, it stops clock outputs (except 2Q0
and 2Q1) in a LOW state (for PE = H or M) – 2Q0, and 2Q1 may be used as
the feedback signal to maintain phase lock. When TEST is held at MID level
and sOE# is HIGH, the nF[1:0] pins act as output disable controls for individual
banks when nF[1:0] = LL. Set sOE# LOW for normal operation.
Selects Positive or Negative Edge Control and High or Low Output Drive
Strength.
When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock, respectively. When at MID level,
the output drive strength is increased and the outputs synchronize with the
positive edge of the reference clock (see
Table 7
on page 4).
Select Frequency and Phase of the Outputs
(see
Table 2, Table 3, Table 4
on page 4,
Table 5
on page 4, and
Table 6
on page 4).
Selects VCO Operating Frequency Range
(see
Table 5
on page 4)
Four Banks of Two Outputs
(see
Table 2, Table 3,
and
Table 4
on page 4)
Description
22
sOE#
I, PD
Two-level
4
PE/HD
I, PU
Three-level
24, 23, 26,
25, 1, 32, 3,
2
31
nF[1:0]
I
Three-level
FS
I
O
Three-level
LVTTL
19, 20, 15,
nQ[1:0]
16, 10, 11, 6,
7
21
12
5
14,30
8,9,17,18,28
V
DDQ1[2]
PWR
V
DDQ3[2]
PWR
V
DDQ4[2]
PWR
V
DD[2]
V
SS
PWR
PWR
Power
Power
Power
Power
Power
Power Supply for Bank 1 and Bank 2 Output Buffers
(see
Table 8
on page
4 for supply level constraints).
Power Supply for Bank 3 Output Buffers
(see
Table 8
on page 4 for supply
level constraints).
Power Supply for Bank 4 Output Buffers
(see
Table 8
on page 4 for supply
level constraints).
Power Supply for Internal Circuitry
(see
Table 8
on page 4 for supply level
constraints).
Ground
Table 3. Output Divider Settings — Bank 4
4F[1:0]
LL
Other
[4]
M — Bank4 Output Divider
2
1
Device Configuration
The outputs of the CY7B9950 can be configured to run at
frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output
dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in
Table 2
and
Table 3,
respectively.
Table 2. Output Divider Settings — Bank 3
3F[1:0]
LL
HH
Other
[4]
K — Bank3 Output Divider
2
4
1
The three-level FS control pin setting determines the nominal
operating frequency range of the divide-by-one outputs of the
device. The CY7B9950 PLL operating frequency range that cor-
responds to each FS level is given in
Table 4
on page 4.
Notes
1. “PD” indicates an internal pull-down and “PU” indicates an internal pull-up. “3” indicates a three-level input buffer
2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic are cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
4. These states are used to program the phase of the respective banks (see
Table 6
on page 4).
Document #: 38-07338 Rev. *D
Page 3 of 12
[+] Feedback
CY7B9950
Table 4. Frequency Range Select
FS
L
M
H
PLL Frequency Range
24 to 50 MHz
48 to 100 MHz
96 to 200 MHz
the t
U
value is: t
U
= 1 / (f
NOM
x MF), where MF is a multiplication
factor, which is determined by the FS setting as indicated in
Table 5.
Table 5. MF Calculation
FS
L
M
H
MF
32
16
8
f
NOM
at which t
U
is 1.0 ns(MHz)
31.25
62.5
125
The selectable output skew is in discrete increments of time units
(t
U
).The value of t
U
is determined by the FS setting and the
maximum nominal frequency. The equation used to determine
Table 6. Output Skew Settings
nF[1:0]
LL
[5]
LM
LH
ML
MM
MH
HL
HM
HH
Skew (1Q[0:1],2Q[0:1])
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
+1t
U
+2t
U
+3t
U
+4t
U
Skew (3Q[0:1])
Divide By 2
–6t
U
–4t
U
–2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Divide By 4
Skew (4Q[0:1])
Divide By 2
v6t
U
–4t
U
v2t
U
Zero Skew
+2t
U
+4t
U
+6t
U
Inverted
[6]
In addition to determining whether the outputs synchronize to the
rising or the falling edge of the reference signal, the 3-level
PE/HD pin controls the output buffer drive strength as indicated
in
Table 7.
The CY7B9950 features split power supply buses for Banks 1
and 2, Bank 3 and Bank 4, which enables the user to obtain both
3.3V and 2.5V output signals from one device. The core power
supply (VDD) must be set a level that is equal or higher than on
any one of the output power supplies.
Table 7. PE/HD Settings
PE/HD
L
M
H
Synchronization
Negative
Positive
Positive
Output Drive Strength
[7]
Low Drive
High Drive
Low Drive
Governing Agencies
The following agencies provide specifications that apply to the
CY7B9950. The agency name and relevant specification is listed
below.
Table 9. Governing Agencies and Specifications
Agency Name
JEDEC
IEEE
UL-194_V0
MIL
Specification
JESD 51 (Theta JA)
JESD 65 (Skew, Jitter)
1596.3 (Jitter Specs)
94 (Moisture Grading)
883E Method 1012.1 (Therma Theta JC)
Table 8. Power Supply Constraints
V
DD
3.3V
2.5V
V
DDQ1
[8]
3.3V or 2.5V
2.5V
V
DDQ3
[8]
3.3V or 2.5V
2.5V
V
DDQ4
[8]
3.3V or 2.5V
2.5V
Notes:
5. LL disables outputs if TEST = MID and sOE# = HIGH.
6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE/HD = HIGH or MID and sOE# disables them LOW when PE/HD = LOW.
7. Please refer to “DC Parameters” section for I
OH
/I
OL
specifications.
8. V
DDQ1/3/4
must not be set at a level higher than that of V
DD
. They can be set at different levels from each other, e.g., V
DD
= 3.3V, V
DDQ1
= 3.3V, V
DDQ3
= 2.5V and
V
DDQ4
= 2.5V.
Document #: 38-07338 Rev. *D
Page 4 of 12
[+] Feedback
CY7B9950
Absolute Maximum Conditions
Parameter
V
DD
V
DD
V
IN(MIN)
V
IN(MAX)
T
S
T
A
T
J
Ø
JC
Ø
JA
ESD
HBM
UL-94
MSL
F
IT
Description
Operating Voltage
Operating Voltage
Input Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability Rating
Moisture Sensitivity Level
Failure in Time
Manufacturing Testing
Condition
Functional @ 2.5V ± 5%
Functional @ 3.3V ± 10%
Relative to V
SS
Relative to V
DD
Non-functional
Functional
Functional
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
At 1/8 in.
Min
2.375
2.97
V
SS
– 0.3
–
–65
–40
–
–
–
2000
V–0
1
10
ppm
Max
2.625
3.63
–
V
DD
+ 0.3
+150
+85
155
42
105
–
Unit
V
V
V
V
°C
°C
°C
°C/W
°C/W
V
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
DC Electrical Specifications at 2.5V
Parameter
V
DD
V
IL
V
IH
V
IHH
[9]
Description
2.5 Operating Voltage
Input LOW Voltage
Input HIGH Voltage
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
Input Leakage Current
3-Level Input DC Current
2.5V ± 5%
Condition
REF, FB and sOE# Inputs
Min
2.375
–
1.7
Max
2.625
0.7
–
Unit
V
V
V
V
V
V
μA
μA
μA
μA
μA
μA
V
V
V
V
mA
mA
pF
V
IMM[9]
V
ILL[9]
I
IL
I
3
3-Level Inputs
–
V
DD
– 0.4
(TEST, FS, nF[1:0], PE/HD) (These pins V /2 – 0.2 V /2 + 0.2
DD
are normally wired to V
DD
, GND or uncon-
DD
–
0.4
nected.)
V
IN
= V
DD
/G
ND
,
V
DD
= max. (REF and FB inputs)
HIGH, V
IN
= V
DD
MID, V
IN
= V
DD
/2
LOW, V
IN
= V
SS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV,
PE/HD)
–5
–
–50
–200
–25
–
–
–
2.0
2.0
–
150
4
5
200
50
–
–
100
0.4
0.4
–
–
2
I
PU
I
PD
V
OL
V
OH
I
DDQ
I
DD
C
IN
Input Pull-up Current
Input Pull-down Current
Output LOW Voltage
Output HIGH Voltage
V
IN
= V
SS
, V
DD
= max.
V
IN
= V
DD
, V
DD
= max., (sOE#)
I
OL
= 12 mA (PE/HD = L/H), (nQ[0:1])
I
OL
= 20 mA (PE/HD = MID), (nQ[0:1])
I
OH
= –12 mA (PE/HD = L/H), (nQ[0:1])
I
OH
= –20 mA (PE/HD = MID), (nQ[0:1])
V
DD
= max., TEST = MID, REF = LOW,
sOE# = LOW, outputs not loaded
At 100 MHz
Quiescent Supply Current
Dynamic Supply Current
Input Pin Capacitance
Note
9. These inputs are normally wired to V
DD
, GND or unconnected. Internal termination resistors bias unconnected inputs to V
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