MOSEL VITELIC
Product List
MSU2032L16
, low working voltage 16 MHz ROM less MCU
MSU2032C16
, 16 MHz ROM less MCU
MSU2032C25
, 25 MHz ROM less MCU
MSU2032C40
, 40 MHz ROM less MCU
MSU2052L16
, low working voltage 16 MHz 4 KB internal ROM MCU
MSU2052C16
, 16 MHz 4 KB internal ROM MCU
MSU2052C25
, 25 MHz 4 KB internal ROM MCU
MSU2052C40
, 40 MHz 4 KB internal ROM MCU
MSU2052/U2032
Description
The MVI MSU2052 series product is an 8 - bit
single chip microcontroller. It provides hardware
features and a powerful instruction set, neces-
sary to make it a versatile and cost effective
controller for those applications demand up to
32 I/O pins or need up to 64 K byte external
memory either for program or for data or mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications,
and full duplex UART.
Features
Working voltage : L series at 2.7V through 4.5V
while S & C series at 4.5 V through 5.5 V
General 80C51 family compatible
64 K byte External Memory Space
8 K byte ROM
256 byte data RAM
Three 16 bit Timers/Counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Working at 16/25/40 MHz Clock
Ordering Information
MSU2032ihhk
MSU2052ihh - yyyk
i: process identifier {L, C}.
hh: working clock in MHz {16, 25, 40}.
yyy: production code {001, ..., 999}
k: package type postfix {as below table}.
P in/Pa d
Postfix
bla nk
P
J
Q
U
Pa ck age
d ice
4 0L P DIP
4 4L P LCC
4 4L P QFP
4 4L L QFP
Configura tion
p ag e 18
pa ge 2
pa ge 2
pa ge 2
pa ge 2
Dime ns ion
p ag e 18
p ag e 14
p ag e 15
p ag e 16
p ag e 17
L ogo Siz e at
Top Ma r ki ng
-
5 .0 x 4 .2 mm
4 .5 x 3 .8 mm
2 .8 x 2 .4 mm
2 .8 x 2 .4 mm
Cross Reference
M.V.I.
W.B.
Philips
L.G.
Intel
CCL. itri
Atmel
MSU2052
W78C52
80C52
G MS80C502
80C52
CIC80520
AT80C52
MSU2032
W78C32
80C32
G MS80C302
80C32
- -- --
AT80C32
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Rev. 1.0 February 1998
1
MOSEL VITELIC
Pin Descriptions
40 PDIP
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Dice
Pad#
39
40
41
42
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15~17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37,38
44 LQFP
Pin#
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
44 PQFP
Pin#
40
41
42
43
44
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
18
19
20
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
44 PLCC
Pin#
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
40
41
42
43
44
Symbol
T2EX/P1.0
T2/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
RXD/P3.0
TXD/P3.1
#INT0/P3.2
#INT1/P3.3
T0/P3.4
T1/P3.5
#WR/P3.6
#RD/P3.7
XTAL2
XTAL1
VSS
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
A12/P2.4
A13/P2.5
A14/P2.6
A15/P2.7
#PSEN
ALE
#EA
AD7/P0.7
AD6/P0.6
AD5/P0.5
AD4/P0.4
AD3/P0.3
AD2/P0.2
AD1/P0.1
AD0/P0.0
VDD
L
H
L
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
L/-
L/-
L/-
L/-
Active I/O
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
Names
bit 0 of Port 1 & timer 2
MSU2052/U2032
bit 1 of Port 1 & timer control
bit 2 of Port 1
bit 3 of Port 1
bit 4 of Port 1
bit 5 of Port 1
bit 6 of Port 1
bit 7 of Port 1
Reset
bit 0 of Port 3 & Receive data
bit 1 of Port 3 & Transmit data
bit 2 of Port 3 & low true Interrupt 0
bit 3 of Port 3 & low true Interrupt 1
bit 4 of Port 3 & Timer 0
bit 5 of Port 3 & Timer 1
bit 6 of Port 3 & Write (low enable)
bit 7 of Port 3 & Read (low enable)
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of Port 2 & Address 8
bit 1 of Port 2 & Address 9
bit 2 of Port 2 & Address 10
bit 3 of Port 2 & Address 11
bit 4 of Port 2 & Address 12
bit 5 of Port 2 & Address 13
bit 6 of Port 2 & Address 14
bit 7 of Port 2 & Address 15
Program store enable (low enable)
Address latch enable
External access first 8 KB memory
bit 7 of Port 0 & Address or Data 7
bit 6 of Port 0 & Address or Data 6
bit 5 of Port 0 & Address or Data 5
bit 4 of Port 0 & Address or Data 4
bit 3 of Port 0 & Address or Data 3
bit 2 of Port 0 & Address or Data 2
bit 1 of Port 0 & Address or Data 1
bit 0 of Port 0 & Address or Data 0
Drive Voltage, +3 Vcc (or +5 Vcc)
Rev. 1.0 February 1998
4
MOSEL VITELIC
Pin Descriptions
Vss
Circuit ground potential.
VDD
+3V (or +5 V) power supply during operation.
PORT 0
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory.
It also contains the timer 2 & its control pins.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance.
PORT 2
Port 2 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance. It also emit the high-order
address byte when accessing external memory.
PORT 3
Port 3 is an 8-bit quasi-bidirectinal I/O port with internal
pull-up resistance. It also contains the interrupt, timer,
serial port and #RD as well as #WR pins that are used
by various options. The output latch corresponding to a
secondary function must be programmed to one (1) for
that function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
- RXD/data (P3.0). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data
output (asynchronous) or data output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.4). Input to counter 1.
- #WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- #RD (P3.7). The read control signal enables External
Data Memory to Port 0.
RES
A high on this pin for two machine cycles (24 clocks)
while the oscillator is running, resets the device. The
data in RAM is preserved when reset signals - reset
does not clear the data in RAM.
ALE
Provides Address Latch Enable output used for latching
the address into external memory during normal
operation.
#PSEN
The Program Store Enable output is a control signal
that enables the external Program Memory to the bus
during normal fetch operations.
MSU2052/U2032
#EA
When held at a TTL high level, the MSU2052 executes
instructions from the internal ROM when the PC is less
than 4096. When held at a TTL low level, the
MSU2052 fetches all instuctions from external Program
Memory.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
Terms
Idle Mode
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing
instructions. In Idle mode (IDL=1), the oscillator
continues to run and the interrput, and timer blocks
continue to be clocked but the clock signal is gated off
to the CPU. The activities of the CPU no longer exist
unless waiting for an interrupt request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
-There are three ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 oscillator periods) to complete the reset. All
SFR and PC value will be cleared to reset value.
3) By one of CLK, DATA, PORT 2.0-2.7 transition to
low (falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
Rev. 1.0 February 1998
5
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