XC17V01SO20I datasheet, PDF - EEWORLD Datasheet

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XC17V01SO20I: Description4M X 1 CONFIGURATION MEMORY, PQFP44; Categorystorage storage; File Size313KB，15 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC17V01SO20I Overview

4M X 1 CONFIGURATION MEMORY, PQFP44

XC17V01SO20I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	SOIC
package instruction	PLASTIC, SOP-20
Contacts	20
Reach Compliance Code	_compli
ECCN code	3A991.B.1.A
Maximum clock frequency (fCLK)	15 MHz
I/O type	COMMON
JESD-30 code	R-PDSO-G20
JESD-609 code	e0
length	12.8 mm
memory density	1048576 bi
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Humidity sensitivity level	3
Number of functions	1
Number of terminals	20
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX1
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP20,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.65 mm
Maximum standby current	0.001 A
Maximum slew rate	0.015 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
Base Number Matches	1

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —

XC17V00 Series Configuration PROMs

DS073 (v2.0) April 7, 2014

Product Specification

Features

•

One-time programmable (OTP) read-only memory

designed to store configuration bitstreams of

Xilinx® FPGA devices

Simple interface to the FPGA

Cascadable for storing longer or multiple bitstreams

Programmable reset polarity (active High or active

Low) for compatibility with different FPGA solutions

Low-power CMOS floating-gate process

3.3V supply voltage

Guaranteed 20 year life data retention

•

Available in compact plastic packages: VQ44, PC44,

PC20, VO8, and SO20

(1)

Programming support by leading programmer

manufacturers

Design support using the ISE® Foundation™ and

ISE WebPACK™ software

Dual configuration modes for the XC17V16 and

XC17V08

(1)

devices

♦

•

Serial slow/fast configuration (up to 20 Mb/s)

Parallel (up to 160 Mb/s at 20 MHz)

Description

Xilinx introduces the high-density XC17V00 family of

configuration PROMs which provide an easy-to-use, cost-

effective method for storing large Xilinx FPGA configuration

bitstreams. Initial devices in the 3.3V family are available in

16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See

Figure 1

and

Figure 2

for simplified block diagrams of the XC17V00

family.

The XC17V00 PROM can configure a Xilinx FPGA using

the FPGA serial configuration mode interface. When the

FPGA is in Master Serial mode, it generates a configuration

clock that drives the PROM. A short access time after the

rising clock edge, data appears on the PROM DATA output

pin that is connected to the FPGA DIN pin. The FPGA

generates the appropriate number of clock pulses to

complete the configuration. Once configured, it disables the

PROM. When the FPGA is in Slave Serial mode, the PROM

and the FPGA must both be clocked by an incoming signal.

The XC17V08

(1)

and XC17V16 PROM can optionally

configure a Xilinx FPGA using the FPGA Parallel

(SelectMAP) configuration mode interface. When the FPGA

is in Master SelectMAP mode, the FPGA generates the

configuration clock that drives the PROM.

When the FPGA is in Slave SelectMAP mode, an external,

free-running oscillator generates the configuration clock

that drives the PROM and the FPGA. After the rising

configuration clock (CCLK) edge, data is available on the

PROMs DATA (D0-D7) pins. The data is clocked into the

FPGA on the following rising edge of the CCLK (Figure

3).

Multiple PROMs can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family.

For device programming, either the Xilinx ISE Foundation or

ISE WebPACK software compiles the FPGA design file into

a standard Hex format, which is then transferred to most

commercial PROM programmers.

1. Specific part number and package combinations have been discontinued. Refer to

XCN07010.

Discontinued part number and package combinations

remain in this data sheet for reference.

other countries. All other trademarks are the property of their respective owners.

DS073 (v2.0) April 7, 2014

Product Specification

www.xilinx.com

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