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FEATURES
Fast Throughput Rate: 1 MSPS
Specified for V
DD
of 3 V and 5 V
Low Power at Max Throughput Rate:
3.75 mW Max at 833 kSPS with 3 V Supplies
9 mW Max at 1 MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70 dB SINAD at 300 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface—SPI
TM
/QSPI
TM
MICROWIRE
TM
/DSP Compatible
Power-Down Mode: 1 A Max
8-Lead SOIC and SOIC Packages
APPLICATIONS
Transducer Interface
Battery-Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
Differential Input, 1 MSPS
12-Bit ADC in SOIC-8 and SO-8
AD7450
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN+
T/H
V
IN–
V
REF
12-BIT SUCCESSIVE
APPROXIMATION
ADC
AD7450
SCLK
CONTROL
LOGIC
SDATA
CS
GND
The AD7450 is a 12-bit, high-speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
fully differential analog input. It operates from a single 3 V or 5 V
power supply and features throughput rates up to 833 kSPS or
1 MSPS, respectively.
This part contains a low noise, wide bandwidth, differential track-
and-hold amplifier (T/H) that can handle input frequencies in
excess of 1 MHz with the –3 dB point typically being 20 MHz.
The reference voltage for the AD7450 is applied externally to the
V
REF
pin and can be varied from 100 mV to 3.5 V, depending
on the power supply and what suits the application. The value of
the reference voltage determines the common-mode voltage
range of the part. With this truly differential input structure and
variable reference input, the user can select a variety of input
ranges and bias points.
The conversion and data acquisition processes are controlled
using
CS
and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
on the falling edge of
CS,
and the conversion is also initiated at
this point.
The SAR architecture of this part ensures that there are no
pipeline delays.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
The AD7450 uses advanced design techniques to achieve low
power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS
1. Operation with either 3 V or 5 V power supplies.
2. High throughput with low power consumption. With a 3 V
supply, the AD7450 offers 3.75 mW max power consumption
for 833 kSPS throughput.
3. Fully differential analog input.
4. Flexible power/serial clock speed management. The conversion
rate is determined by the serial clock, allowing the power
to be reduced as the conversion time is reduced through
the serial clock speed increase. This part also features a
shutdown mode to maximize power efficiency at lower
throughput rates.
5. Variable voltage reference input.
6. No pipeline delay.
7. Accurate control of the sampling instant via a
CS
input and
once-off conversion control.
8. ENOB > 8 bits typically with 100 mV reference.
Rev. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/461/3113
© Analog Devices, Inc., 2002
AD7450–SPECIFICATIONS
1
(V
Parameter
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) Ratio
(SINAD)
3
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise
3
Intermodulation Distortion (IMD)
3
Second Order Terms
Third Order Terms
Aperture Delay
3
Aperture Jitter
3
Full Power Bandwidth
3
Power Supply Rejection Ratio
(PSRR)
3, 4
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
3
Differential Nonlinearity (DNL)
3
Zero Code Error
3
= 2.7 V to 3.3 V, f
SCLK
= 15 MHz, f
S
= 833 kSPS, V
REF
= 1.25 V, F
IN
= 200 kHz;
V
DD
= 4.75 V to 5.25 V, f
SCLK
= 18 MHz, f
S
= 1 MSPS, V
REF
= 2.5 V, F
IN
= 300 kHz; V
CM2
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
DD
Conditions/Comments
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V, –80 dB typ
V
DD
= 3 V, –78 dB typ
V
DD
= 5 V, –82 dB typ
V
DD
= 3 V, –80 dB typ
A Version
70
68
–75
–73
–75
–73
–85
–85
10
50
20
2.5
–87
12
±
2
B Version
70
68
–75
–73
–75
–73
–85
–85
10
50
20
2.5
–87
12
±
1
±
1
±
3
±
6
±
3
±
6
±
3
±
6
V
IN+
– V
IN–
V
CM
±
V
REF
/2
V
CM
±
V
REF
/2
±
1
20
6
Unit
dB min
dB min
dB max
dB max
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
dB typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
V
V
V
µA
max
pF typ
pF typ
@ –3 dB
@ –0.1 dB
Positive Gain Error
3
Negative Gain Error
3
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
V
IN+
V
IN–
DC Leakage Current
Input Capacitance
REFERENCE INPUT
V
REF
Input Voltage
Guaranteed No Missed
Codes to 12 Bits
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
2
V
REF5
–1/+2
±
3
±
6
±
3
±
6
±
3
±
6
V
IN+
– V
IN–
V
CM
±
V
REF
/2
V
CM
±
V
REF
/2
±
1
20
6
V
CM2
= V
REF
V
CM2
= V
REF
When in Track
When in Hold
5 V supply (± 1% tolerance for
specified performance)
3 V supply (± 1% tolerance for
specified performance)
2.5
6
1.25
7
±
1
15
2.4
0.8
±
1
10
2.8
2.4
0.4
±
1
10
Two’s
Complement
2.5
6
1.25
7
±
1
15
2.4
0.8
±
1
10
2.8
2.4
0.4
±
1
10
Two’s
Complement
V
V
µA
max
pF typ
V min
V max
µA
max
pF max
V min
V min
V max
µA
max
pF max
DC Leakage Current
V
REF
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN8
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
8
Output Coding
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
= 5 V, I
SOURCE
= 200
µA
V
DD
= 3 V, I
SOURCE
= 200
µA
I
SINK
= 200
µA
–2–
Rev. A
AD7450
Parameter
CONVERSION RATE
Conversion Time
Track-and-Hold
Acquisition Time
3, 8
Throughput Rate
9
POWER REQUIREMENTS
V
DD
I
DD10, 11
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Conditions/Comments
888 ns with an 18 MHz SCLK
1.07
µs
with a 15 MHz SCLK
Sine Wave Input
V
DD
= 5 V
V
DD
= 3 V
Range: 3 V
±
10%; 5 V
±
5%
V
DD
= 3 V/5 V SCLK; ON or OFF
V
DD
= 5 V; f
SAMPLE
= 1 MSPS
V
DD
= 3 V; f
SAMPLE
= 833 kSPS
SCLK ON or OFF
V
DD
= 5 V; f
SAMPLE
= 1 MSPS;
1.38 mW typ for 100 KSPS
10
V
DD
= 3 V; f
SAMPLE
= 833 kSPS;
0.53 mW typ for 100 KSPS
10
V
DD
= 5 V; SCLK ON or OFF
V
DD
= 3 V; SCLK ON or OFF
A Version
16
200
1
833
3/5
0.5
1.8
1.25
1
9
3.75
5
3
B Version
16
200
1
833
3/5
0.5
1.8
1.25
1
9
3.75
5
3
Unit
SCLK Cycles
ns max
MSPS max
kSPS max
V min/max
mA typ
mA max
mA max
µA
max
mW max
mW max
µW
max
µW
max
Full Power-Down Mode
NOTES
1
Temperature range is as follows: A and B Versions: –40°C to +85°C.
2
Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9.
3
See Terminology section.
4
A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto V
DD
. A 2.2 nF capacitor is used to decouple V
DD
to GND.
5
If the input spans of V
IN+
and V
IN–
are both V
REF
, and they are 180° out of phase, the differential voltage is 2 V
REF
.
6
The AD7450 is functional with a reference input from 100 mV and for V
DD
= 5 V, the reference can range up to 3.5 V (see References section).
7
The AD7450 is functional with a reference input from 100 mV and for V
DD
= 3 V, the reference can range up to 2.2 V (see References section).
8
Sample tested @ 25°C to ensure compliance.
9
See Serial Interface section.
10
See Power Versus Throughput Rate section.
11
Measured with a midscale dc input.
Rev. A
–3–
AD7450
TIMING SPECIFICATIONS
1, 2
f
SCLK
= 18 MHz, f
S
= 1 MSPS, V
REF
= 2.5 V; V
CM
Limit at T
MIN
, T
MAX
3V
5V
50
15
16 t
SCLK
1.07
25
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
50
18
16 t
SCLK
0.88
25
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
Parameter
f
SCLK4
t
CONVERT
t
QUIET
t
1
t
2
t
3 5
t
4 5
t
5
t
6
t
7
t
8 6
t
POWER-UP7
3
(V
DD
= 2.7 V to 3.3 V, f
SCLK
= 15 MHz, f
S
= 833 kSPS, V
REF
= 1.25 V; V
DD
= 4.75 V to 5.25 V,
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Unit
kHz min
MHz max
µs
max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs
max
Description
t
SCLK
= 1/f
SCLK
SCLK = 15 MHz, 18 MHz
Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of
CS
Minimum
CS
Pulsewidth
CS
Falling Edge to SCLK Falling Edge Setup Time
Delay from
CS
Falling Edge until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State Enabled
SCLK Falling Edge to SDATA Three-State Enabled
Power-Up Time from Full Power-Down
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 1 and the Serial Interface section.
3
Common-mode voltage.
4
Mark/space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V, and the time for an output to cross
0.4 V or 2.0 V for V
DD
= 3 V.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7
See Power-Up Time section.
Specifications subject to change without notice.
t
1
CS
t
CONVERT
t
2
SCLK
1
2
3
4
5
13
14
15
16
t
5
t
7
t
3
SDATA
0
0
0
0
t
6
t
8
t
QUIET
t
4
DB11
DB10
DB2
DB1
DB0
THREE-STATE
4 LEADING ZEROS
Figure 1. Serial Interface Timing Diagram
–4–
Rev. A
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