E2U0013-28-81
¡ Semiconductor
MSM7508B/7509B
¡ Semiconductor
Single Rail CODEC
This version: Aug. 1998
MSM7508B/7509B
Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM7508B and MSM7509B are single-channel CODEC CMOS ICs for voice signals ranging
from 300 to 3400 Hz. These devices contain filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, these devices are
optimized for telephone terminals in ISDN and digital wireless systems.
The MSM7508B/MSM7509B are the transmission-clocks extended versions of the MSM7508/
MSM7509. It is recommended to use the MSM7508/MSM7509 for the transmission clocks of 64,
128, 256kHz.
FEATURES
• Single power supply: +5 V
±5%
• Low power consumption
Operating mode:
17.5 mW Typ.
37 mW Max.
Power down mode:
1.5 mW Typ.
3 mW Max.
• ITU-T Companding law
MSM7508B:
m-law
MSM7509B:
A-law
• Built-in PLL eliminates a master clock
• Transmission clock: 64/128/256/512/1024/2048 kHz
96/192/384/768/1536/1544/200 kHz
• Adjustable transmit gain
• Built-in reference voltage supply
• Package options:
16-pin plastic DIP (DIP16-P-300-2.54-W1)
(Product name : MSM7508BRS)
(Product name : MSM7509BRS)
24-pin plastic SOP (SOP24-P-430-1.27-K)
(Product name : MSM7508BGS-K)
(Product name : MSM7509BGS-K)
28-pin plastic QFJ (PLCC) (QFJ28-P-S450-1.27) (Product name : MSM7508BJS)
(Product name : MSM7509BJS)
Note:
The product names are indicated in PIN CONFIGURATION.
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¡ Semiconductor
MSM7508B/7509B
PIN AND FUNCTIONAL DESCRIPTIONS
AIN+, AIN–, GSX
Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp and is used to adjust the level, as shown below.
When not using AIN– and AIN+, connect AIN– to GSX and AIN+ to SG. During power saving
and power down modes, the GSX output is in a high impedance state.
1) Inverting input type
C1
Analog input
R1
GSX
AIN–
AIN+
SG
R1 : variable
R2 > 20 kW
C1 > 1/(2
¥
3.14
¥
30
¥
R1)
Gain = R2/R1
£
10
R2
–
+
2) Non inverting input type
C2
Analog input
R5
R4
R3
AIN+
AIN–
GSX
SG
+
–
R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2
¥
3.14
¥
30
¥
R5)
Gain = 1 + R4 / R3
£
10
AG
Analog signal ground.
AOUT
Analog output.
The output signal amplitude is a maximum of 2.4 V
PP
above and below the signal ground voltage
level (V
DD
/2).
The output load resistance is a minimum of 20 kW.
During power saving or power down mode, the output of AOUT is at the voltage level of signal
ground.
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¡ Semiconductor
V
DD
Power supply for +5 V.
PCMIN
MSM7508B/7509B
PCM signal input.
A serial PCM signal input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLOCK signal.
The data rate of the PCM signal is equal to the frequency of the BCLOCK signal.
The PCM signal is shifted at a falling edge of the BCLOCK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.
BCLOCK
Shift clock signal input for the PCMIN and PCMOUT signal.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.
RSYNC
Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLOCK. The frequency should be 8 kHz
±50
ppm to guarantee
the AC characteristics which are mainly frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are
not guaranteed. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to
the power saving state.
XSYNC
Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this transmit
synchronizing signal. This synchronizing signal triggers the PLL and synchronizes all timing
signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLOCK.
The frequency should be 8 kHz
±50
ppm to guarantee the AC characteristics which are mainly
frequency characteristics of the transmit section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 8 to 10 kHz, but the electrical characteristics in this specification are
not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.
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