871S1022EKLF datasheet, PDF - EEWORLD Datasheet

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871S1022EKLF: DescriptionVFQFPN-32, Tray; CategoryThe embedded processor and controller Microcontrollers and processors; File Size937KB，23 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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871S1022EKLF Overview

VFQFPN-32, Tray

871S1022EKLF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	VFQFPN
package instruction	HVQCCN,
Contacts	32
Manufacturer packaging code	NLG32P1
Reach Compliance Code	compliant
ECCN code	EAR99
Samacsys Confidence	3
Samacsys Status	Released
Samacsys PartID	738338
Samacsys Pin Count	33
Samacsys Part Category	Integrated Circuit
Samacsys Package Category	Quad Flat No-Lead
Samacsys Footprint Name	NLG32P1-
Samacsys Released Date	2018-08-14 08:32:40
Is Samacsys	N
JESD-30 code	S-XQCC-N32
JESD-609 code	e3
length	5 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	500 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	25 MHz
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER
Base Number Matches	1

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Differential-to-0.7V Differential PCI Express

™

Jitter Attenuator

ICS871S1022

DATASHEET

Description

IDT’s PLL-based clock generators offer sub-picosecond jitter,

low-skew clock outputs, and edge rates that meet the ever-growing

demands of today’s networking solutions.

The ICS871S1022 is a PLL-based clock generator specifically

designed for PCI Express Clock Generation applications. The device

generates 100MHz, 125MHz, 250MHz or 500MHz from either a

25MHz fundamental mode crystal or a 100MHz recovered clock.

The ICS871S1022 has two modes of operation: (1) high frequency

jitter attenuator and (2) high performance clock synthesizer mode.

When in jitter attenuator mode, the ICS871S1022 is able to both

suppress high frequency noise components and function as a

frequency translator. Designed to receive a jittery and noisy clock

from an external source, the ICS871S1022 uses FemtoClock

technology to clean up the incoming clock and translate the

frequency to one of the four common PCI Express frequencies.

When in synthesizer mode, the device is able to generate high

performance SSC and non-SSC clocks from a low cost external,

25MHz, fundamental mode crystal.

The ICS871S1022 uses FemtoClock

technology to generate low

noise clock outputs capable of providing the seed frequencies for the

common PCI Express link rates.

Features

•

Four 0.7V differential output pairs

One differential clock input pair

CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL

Crystal oscillator interface designed for 25MHz, 18pF parallel

resonant crystal

RMS phase jitter at 100MHz, using a 25MHz crystal

(12kHz – 20MHz): 0.608ps (typical)

High frequency jitter attenuator mode has high PLL bandwidth

which allows for better input tracking

Supports PCI Express Spread-Spectrum Clocking

PCI Express Gen 1, 2 and 3 jitter compliant

3.3V operating supply voltage

0°C to 70°C ambient operating temperature

Available in lead-free (RoHS 6) package

Pin Assignment

32-Lead VFQFN

5mm x 5mm x 0.925mm package body

K Package

Top View

ICS871S1022EK November 2, 2017

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