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IDT74CV105BPV

Description
Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size95KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74CV105BPV Overview

Processor Specific Clock Generator, 200MHz, PDSO48, SSOP-48

IDT74CV105BPV Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeSSOP
package instructionSSOP,
Contacts48
Reach Compliance Codenot_compliant
ECCN codeEAR99
JESD-30 codeR-PDSO-G48
JESD-609 codee0
length15.875 mm
Humidity sensitivity level1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Maximum output clock frequency200 MHz
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
Master clock/crystal nominal frequency14.31818 MHz
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width7.493 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches1
IDTCV105B
CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
COMMERCIAL TEMPERATURE RANGE
CLOCK GENERATOR FOR
DESKTOP PC PLATFORMS
IDTCV105B
PRELIMINARY
FEATURES:
DESCRIPTION:
4 PLL architecture
Linear frequency programming
Independent frequency programming and SSC control
Band-gap circuit for differential output
High power-noise rejection ratio
66MHz to 533MHz CPU frequency
VCO frequency up to 1.1G
Support index block read/write, single cycle index block read
Programmable REF, 3V66, PCI, 48MHz I/O drive strength
Programmable 3V66 and PCI Skew
Available in SSOP package
IDTCV105B is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/
PCI, SRC, and 48MHz clocks. The dedicated PLL for Serial ATA clock
provides high accuracy frequency. This device also implements Band-gap
referenced I
REF
to reduce the impact of V
DD
variation on differential outputs,
which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high
accuracy output clock. Each CPU, AGP/PCI, SRC clock has its own Spread
Spectrum selection.
KEY SPECIFICATION:
CPU/SRC CLK cycle to cycle jitter < 125ps
SATA CLK cycle to cycle jitter < 125ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error as low as 36 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
EasyN
Programming
CPU CLK
Output Buffers
CPU[1:0]
CPU_ITP
X1
XTAL
Osc Amp
I
REF
REF 1.0
X2
PLL2
SSC
EasyN
Programming
SDATA
SCLK
SM Bus
Controller
3V66/PCI
Output Buffers
PCI[5:0], PCIF[2:0]
3V66[3:0]
PLL3
SSC
V
TT_PWRGD
Watch Dog
Timer
FS[1:0]
Control
Logic
SRC CLK
Output Buffer
SRC
I
REF
48MHz[1:0]
S
EL
24_48#
PLL4
48MHz
Output Buffer
RESET#
OUTPUT TABLE
CPU (Pair)
3
3V66
3
3V66/VCH
1
PCI
6
PCIF
3
REF
2
48MHz
2
24 - 48MHz
0
SRC (Pair)
1
Reset#
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2003 Integrated Device Technology, Inc.
SEPTEMBER 2003
DSC-6392/7
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