ADC101S021
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SNAS307G – JULY 2005 – REVISED JANUARY 2014
ADC101S021 Single Channel, 50 to 200 ksps, 10-Bit A/D Converter
Check for Samples:
ADC101S021
1
FEATURES
Specified Over a Range of Sample Rates.
6-Lead WSON and SOT-23 Packages
Variable Power Management
Single Power Supply with 2.7V - 5.25V Range
SPI™/QSPI™/MICROWIRE/DSP Compatible
DESCRIPTION
The ADC101S021 is a low-power, single channel
CMOS 10-bit analog-to-digital converter with a high-
speed serial interface. Unlike the conventional
practice of specifying performance at a single sample
rate only, the ADC101S021 is fully specified over a
sample rate range of 50 ksps to 200 ksps. The
converter is based upon a successive-approximation
register architecture with an internal track-and-hold
circuit.
The output serial data is straight binary, and is
compatible with several standards, such as SPI™,
QSPI™, MICROWIRE, and many common DSP
serial interfaces.
The ADC101S021 operates with a single supply that
can range from +2.7V to +5.25V. Normal power
consumption using a +3.6V or +5.25V supply is 2.34
mW and 8.9 mW, respectively. The power-down
feature reduces the power consumption to as low as
2.6 µW using a +5.25V supply.
The ADC101S021 is packaged in 6-lead WSON and
SOT-23 packages. Operation over the industrial
temperature range of
−40°C
to +85°C is ensured.
•
•
•
•
•
2
APPLICATIONS
•
•
•
Portable Systems
Remote Data Acquisition
Instrumentation and Control Systems
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright © 2005–2014, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADC101S021
SNAS307G – JULY 2005 – REVISED JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. Key Specifications
VALUE
DNL
INL
SNR
Power Consumption
3.6V Supply
5.25V Supply
+0.16 / -0.09
+0.14 / -0.13
61.6
2.34
8.9
UNIT
LSB (typ)
LSB (typ)
dB (typ)
mW (typ)
mW (typ)
Table 2. Pin-Compatible Alternatives by Resolution and Speed
(1)
Resolution
50 to 200 ksps
12-bit
10-bit
8-bit
(1)
ADC121S021
ADC101S021
ADC081S021
Specified for Sample Rate Range of:
200 to 500 ksps
ADC121S051
ADC101S051
ADC081S051
500 ksps to 1 Msps
ADC121S101
ADC101S101
ADC081S101
All devices are fully pin and function compatible.
Connection Diagram
V
A
GND
V
IN
1
2
3
6
CS
SDATA
SCLK
ADC101S021
5
4
Figure 1. 6-Lead SOT-23 or WSON
See DBV or NGF Package
Block Diagram
10-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
IN
T/H
SCLK
CONTROL
LOGIC
CS
SDATA
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No.
ANALOG I/O
3
DIGITAL I/O
4
2
SCLK
Digital clock input. This clock directly controls the conversion and readout processes.
V
IN
Analog input. This signal can range from 0V to V
A
.
Symbol
Description
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ADC101S021
Copyright © 2005–2014, Texas Instruments Incorporated
ADC101S021
www.ti.com
SNAS307G – JULY 2005 – REVISED JANUARY 2014
PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin No.
ANALOG I/O
5
6
POWER SUPPLY
1
2
PAD
V
A
GND
GND
Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to
GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.
The ground return for the supply and signals.
For package suffix CISD(X) only, it is recommended that the center pad should be connected to ground.
(1) (2) (3)
Symbol
SDATA
CS
Description
Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins.
Absolute Maximum Ratings
Analog Supply Voltage V
A
Voltage on Any Analog Pin to GND
Voltage on Any Digital Pin to GND
Input Current at Any Pin
Package Input Current
ESD Susceptibility
(6)
Human Body Model
Machine Model
Junction Temperature
Storage Temperature
(1)
(4)
(4)
−0.3V
to 6.5V
−0.3V
to (V
A
+0.3V)
−0.3V
to 6.5V
±10 mA
±20 mA
See
(5)
Power Consumption at T
A
= 25°C
3500V
300V
+150°C
−65°C
to +150°C
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
When the input voltage at any pin exceeds the power supply (that is, V
IN
< GND or V
IN
> V
A
), the current at that pin should be limited to
10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an
input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the V
A
pin. The current into the V
A
pin is
limited by the Analog Supply Voltage specification.
The absolute maximum junction temperature (T
J
max) for this device is 150°C. The maximum allowable power dissipation is dictated by
T
J
max, the junction-to-ambient thermal resistance (θ
JA
), and the ambient temperature (T
A
), and can be calculated using the formula
P
D
max = (T
J
max
−
T
A
) /
θ
JA
. The values for maximum power dissipation listed above will be reached only when the device is operated
in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
(1) (2)
Operating Ratings
V
A
Supply Voltage
Operating Temperature Range
Digital Input Pins Voltage Range
(regardless of supply voltage)
Analog Input Pins Voltage Range
Clock Frequency
Sample Rate
(1)
−40°C ≤
T
A
≤
+85°C
+2.7V to +5.25V
−0.3V
to 5.25V
0V to V
A
25 kHz to 20 MHz
up to 1Msps
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Copyright © 2005–2014, Texas Instruments Incorporated
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ADC101S021
SNAS307G – JULY 2005 – REVISED JANUARY 2014
www.ti.com
Package Thermal Resistance
Package
6-lead WSON
6-lead SOT-23
θ
JA
94°C / W
265°C / W
Soldering process must comply with Reflow Temperature Profile specifications. Refer to
http://www.ti.com/packaging.
(1)
(1)
Reflow temperature profiles are different for lead-free and non-lead-free packages.
4
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ADC101S021
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SNAS307G – JULY 2005 – REVISED JANUARY 2014
(1) (2)
ADC101S021 Converter Electrical Characteristics
The following specifications apply for V
A
= +2.7V to 5.25V, f
SCLK
= 1 MHz to 4 MHz, f
SAMPLE
= 50 ksps to 200 ksps, C
L
= 15
pF, unless otherwise noted.
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25°C.
Symbol
Parameter
Conditions
Typical
Limits
(2)
Units
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
V
A
= +2.7 to +3.6V
INL
Integral Non-Linearity
V
A
= +4.75 to +5.25V
V
A
= +2.7 to +3.6V
DNL
Differential Non-Linearity
V
A
= +4.75 to +5.25V
V
OFF
GE
Offset Error
Gain Error
V
A
= +2.7V to +3.6V
V
A
= +4.75 to +5.25V
V
A
= +2.7V to +3.6V
V
A
= +4.75 to +5.25V
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz,
−0.02
dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz,
−0.02
dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz,
−0.02
dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz,
−0.02
dBFS
V
A
= +2.7 to 5.25V
f
IN
= 100 kHz,
−0.02
dBFS
V
A
= +5.25V
f
a
= 103.5 kHz, f
b
= 113.5 kHz
V
A
= +5.25V
f
a
= 103.5 kHz, f
b
= 113.5 kHz
V
A
= +5V
V
A
= +3V
+0.14
−0.13
+0.14
−0.13
+0.12
−0.07
+0.16
−0.09
−0.09
−0.06
−0.27
±0.7
±0.7
±0.6
±0.6
±0.7
±1.0
Bits
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (min)
LSB (min)
LSB (max)
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
SINAD
SNR
THD
SFDR
ENOB
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Effective Number of Bits
Intermodulation Distortion, Second
Order Terms
Intermodulation Distortion, Third Order
Terms
-3 dB Full Power Bandwidth
61.5
61.6
−79
79
9.9
−83
−82
11
8
0 to V
A
±1
Track Mode
Hold Mode
V
A
= +5.25V
V
A
= +3.6V
V
A
= +5V
V
A
= +3V
V
IN
= 0V or V
A
±0.1
2
30
4
2.4
2.1
0.8
0.4
±1
4
60.7
61
−72.5
74
9.8
dB (min)
dB (min)
dB (max)
dB (min)
Bits (min)
dB
dB
MHz
MHz
V
µA (max)
pF
pF
V (min)
V (min)
V (max)
V (max)
µA (max)
pF (max)
IMD
FPBW
ANALOG INPUT CHARACTERISTICS
V
IN
I
DCL
C
INA
Input Range
DC Leakage Current
Input Capacitance
DIGITAL INPUT CHARACTERISTICS
V
IH
V
IL
I
IN
C
IND
(1)
(2)
Input High Voltage
Input Low Voltage
Input Current
Digital Input Capacitance
Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).
Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
Copyright © 2005–2014, Texas Instruments Incorporated
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