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EDI88128LPS15NM

Description
Standard SRAM, 128KX8, 15ns, CMOS, CDSO32, CERAMIC, SOJ-32
Categorystorage    storage   
File Size464KB,9 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

EDI88128LPS15NM Overview

Standard SRAM, 128KX8, 15ns, CMOS, CDSO32, CERAMIC, SOJ-32

EDI88128LPS15NM Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicrosemi
Parts packaging codeSOJ
package instructionSOJ, SOJ32,.44
Contacts32
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Is SamacsysN
Maximum access time15 ns
I/O typeCOMMON
JESD-30 codeR-CDSO-J32
length21.082 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.44
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height3.937 mm
Maximum standby current0.002 A
Minimum standby current2 V
Maximum slew rate0.3 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.0998 mm
Base Number Matches1
White Electronic Designs
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
CS# and OE# Functions for Bus Control
2V Data Retention (EDI88128LPS)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 128Kx8
Commercial, Industrial and Military Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Ceramic DIP, 400 mil (Package 102)
• 32 pin Ceramic DIP, 600 mil (Package 9)
• 32 lead Ceramic ZIP (Package 100)
• 32 lead Ceramic SOJ (Package 140)
EDI88128CS
• 32 pad Ceramic LCC (Package 141)
• 32 lead Ceramic Flatpack (Package 142)
Single +5V (±10%) Supply OperationThe
EDI88128CS is a high speed, high performance,
128Kx8 megabit density Monolithic CMOS Static
RAM.
The device has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word. An
automatic power down feature permits the on-chip circuitry
to enter a very low standby mode and be brought back into
operation at a speed equal to the address access time.
A Low Power version with 2V Data Retention (EDI88128LPS)
is also available for battery back-up opperation. Military
product is available compliant to MIL-PRF-38535.
* 15ns access time is advanced information, contact factory for availability.
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
32
32
32
32
DIP
SOJ
LCC
FLATPACK
PIN DESCRIPTION
I/O0-7
A0-16
WE#
CS#
OE#
VCC
VSS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power (+5V ±10%)
Ground
Not Connected
32 ZIP
TOP VIEW
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 V
CC
31 A15
30 NC
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
TOP VIEW
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
2 V
CC
4
A15
6
NC
8
WE#
10 A13
12 A8
14 A9
16 A11
18 OE#
20 A10
22 CS#
24 I/O7
26 I/O6
28 I/O5
30 I/O4
32 I/O3
BLOCK DIAGRAM
Memory Array
A
0-16
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
0-7
WE#
CS#
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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