FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12545-1E
8-bit Proprietary Microcontroller
CMOS
F
2
MC-8L MB89960 Series
MB89965/P965A/F969A/
MB89PV960
s
DESCRIPTION
The MB89960 series is a single-chip microcontroller that utilizes the F
2
MC-8L core for low voltage and high speed
performance. The microcontroller contains a range of peripheral functions including timers, a serial interface, I
2
C
interface, A/D converter, and external interrupts. The internal I
2
C interface complies with the SM bus standard
and supports an SM bus battery controller.
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FEATURES
• Range of package options
• QFP and MQFP packages (0.8 mm pitch)
• LQFP package (0.5 mm and 0.65 mm pitch)
•
High speed operation at low voltage
Minimum instruction execution time
=
0.4
µs
(for a 10 MHz oscillation)
•
F
2
MC-8L CPU core
Instruction set optimized for controller applications
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
•
Dual-clock control system
• Main clock : 10 MHz max.
(Four speed settings available, oscillation halts in sub-clock mode)
• Sub-clock : 32.768 kHz (Operation clock for sub-clock mode)
•
•
•
•
Four channels
8/16-bit timer/counter (8-bit
×
2 channels or 16-bit
×
1 channel)
21-bit timebase timer
Clock prescaler (15-bit)
•
Serial I/O
Selectable transfer format (MSB-first or LSB-first) supports communications with a wide range of devices.
•
A/D converter
10-bit
×
4 channels
MB89960 Series
•
External interrupts
• External interrupt 1 (3 channels)
Three independent interrupt inputs can be used to recover from low-power consumption modes (with edge-
detection function)
• External interrupt 2 (1 channel with 8 inputs)
Eight inputs can be used to recover from low-power consumption modes (with “L” level detection function)
•
•
•
•
Low-power consumption modes (standby modes)
Stop mode (As all oscillations halt in sub-clock mode, current consumption falls to almost zero.)
Sleep mode (The CPU stops to reduce the current consumption to approximately 1/3 of normal.)
Clock mode (All operation halts other than the clock prescaler resulting in very low power consumption.)
•
I
2
C interface*
• Supports Intel SM bus and Philips I
2
C bus standards.
• Uses a two-wire data transfer protocol.
•
•
•
•
Max. 35 I/O ports
Output-only ports (N-ch open drain)
General-purpose I/O ports (CMOS)
Output-only ports (CMOS)
:6
: 21
:8
* : I
2
C license
The customer is licensed to use the Philips I
2
C patent when using this product in an I
2
C system that complies
with the Philips I
2
C standard specifications.
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PACKAGE
Plastic LQFP, 48-pin
Plastic QFP, 48-pin
Plastic QFP, 48-pin
(FPT-48P-M05)
(FPT-48P-M13)
(FPT-48P-M16)
Ceramic MQFP, 48-pin
Plastic LQFP, 64-pin
(MQP-48C-P01)
2
(FPT-64P-M09)
MB89960 Series
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PRODUCT LINEUP
Part No.
Prameter
Classification
MB89965
Mass-produced
products
(mask ROM products)
MB89P965A
MB89F969A
MB89PV960
Piggyback/
evaluation product
for testing and
development
32 K
×
8-bit
(External ROM) *
One-time product
Flash product
ROM size
RAM size
16 K
×
8-bit (Internal mask ROM)
512
×
8-bit
Number of instructions
Instruction bit length
Instruction length
Data bit length
Minimum execution time
Interrupt processing time
Output-only ports (N-ch open drain)
60 K
×
8-bit
1024
×
8-bit
: 136
: 8-bit
: 1 to 3 bytes
: 1-, 8-, 16bits
: 0.4
µs
(at 10 MHz)
: 3.6
µs
(at 10 MHz)
: 6 (4 pins are shared with analog inputs)
(2 pins are shared with resource I/O)
:8
: 21 (shared with resource I/O)
35 (max.)
CPU functions
Ports
Output-only ports (CMOS)
General-purpose I/O ports (CMOS)
Total
21-bit
Timebase timer Four interrupt intervals selectable 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms (approx.) (for
main clock)
Watchdog timer
Reset trigger period : 419.4 ms (10 MHz main clock)
500 ms (32.768 MHz sub-clock)
One channel. Supports Intel SM bus (version 1.0) and Philips I
2
C bus standards.
Uses a 2-wire protocol for communications with other devices.
Pe-
riph-
eral
func-
tions
I
2
C interface
Included/Not included
(Specified when order-
ing. See “Ordering In-
formation” for details.)
Included
8/16-bit timer/
counter Timer
2 channel 8-bit timer/counter operation (independent operation clocks for timer 1 and
timer 2) or 16-bit timer/counter operation (operation clock period : 0.8
µs
to 204.8
µs)
can execute an event counter operation and output a square wave using an external
Clock.
1 or 16-bit timer/counter operation mode
8 bits
LSB-first or MSB-first selectable
Transfer clocks : External or three internal clocks (0.8
µs,
3.2
µs,
12.8
µs)
Selectable edge detection (rising, falling, or either edge)
3 independent channels
These can also be used to recover from standby modes (edge detection is still available
in stop mode) .
1 channel with 8 inputs (“L” level interrupts, independent input enable)
This can also be used to recover from standby modes (level detection is still available in
stop mode) .
Serial I/O
External
interrupt 1
(edge)
External
interrupt 2
(level)
(Continued)
3
MB89960 Series
(Continued)
Part No.
Prameter
MB89965
MB89P965A
MB89F969A
MB89PV960
Pe-
riph- A/D converter
eral
func-
tions
15-bit
Clock prescaler
Interrupt interval : 31.25 ms, 0.25 s, 0.50 s, 1.00 s (for a 32.768 kHz sub-clock)
Low power consump-
tion (standby modes)
Process
Operating voltage
Sleep mode, stop mode, and clock mode
CMOS
3.5 V to 5.5 V
4 channel
×
10-bit resolution
A/D conversion time : 15.2
µs
(MB89965, MB89P965A, MB89F969A)
13.2
µs
(MB89PV960)
Continuous activation is available using the output from the 8/16-bit timer/counter or
timebase timer.
Reference voltage input (AVR)
* : Use the MBM27C256A-20TVM as the external ROM (Operating voltage : 4.5 V to 5.5 V)
Note : Unless otherwise stated, clock periods and conversion times are for 10 MHz operation with the main clock
operating at maximum speed.
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PACKAGES AND CORRESPONDING PRODUCTS
Part No.
Package
FPT-48P-M05
FPT-48P-M13
FPT-48P-M16
FPT-64P-M09
MQP-48C-P01
: Available
×
: Not available
×
×
×
×
×
MB89965
MB89P965A
MB89F969A
×
×
×
MB89PV960
×
×
×
×
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MB89960 Series
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DIFFERENCES AMONG PRODUCTS
1.
Memory Space
Please take note of the differences among products before testing and developing software for the MB89960
series.
• The RAM and ROM configurations differ among products.
• If the bottom stack address is set at the top RAM address, this will need to be relocated if changing to a different
product.
2. Current Consumption
• In the case of the MB89PV960, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, one-time PROM and EPROM products will consume more current than mask
ROM products. However, the current consumption in sleep/stop modes is the same.
3. Functional Differences Between MB89960 Series
MB89965/P965A/F969A
Power-on reset delay time
External reset delay time in stop/
sub-clock mode or external
interrupt delay time in main stop
mode
Port pin pull-up resistors
A/D conversion time
I
2
C noise elimination circuit
Regulator stabilization delay time,
regulator recovery time,
oscillation stabilization delay time
Regulator recovery time,
oscillation stabilization delay time
Software-selectable
38 instruction cycles
Always present regardless of ICCR :
DMPB bit setting
MB89PV960
Oscillation stabilization delay time
Oscillation stabilization delay time
Not available
33 instruction cycles
Disabled if ICCR : DMPB bit
=
“1”
4. Mask Options
Functions that can be selected as options and the methods used to specify these options vary by the product.
Before using mask options, check section “
Mask Options”.
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