54242-809-46-1950 datasheet, PDF

54242-809-46-1950: DescriptionBoard Stacking Connector, 46 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Receptacle,; CategoryThe connector The connector; File Size108KB，1 Pages; ManufacturerAmphenol; Websitehttp://www.amphenol.com/

Download Datasheet Parametric View All

54242-809-46-1950 Overview

Board Stacking Connector, 46 Contact(s), 2 Row(s), Male, Straight, 0.1 inch Pitch, Surface Mount Terminal, Locking, Black Insulator, Receptacle,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Objectid	1627215967
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	6.44
body width	0.169 inch
subject depth	0.768 inch
body length	4.6 inch
Body/casing type	RECEPTACLE
Connector type	BOARD STACKING CONNECTOR
Contact to complete cooperation	GOLD (15) OVER NICKEL (50)/NICKEL PALLADIUM GOLD (15) OVER NICKEL (50)
Contact completed and terminated	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact point gender	MALE
Contact material	PHOSPHOR BRONZE
contact mode	RECTANGULAR
Contact style	SQ PIN-SKT
DIN compliance	NO
Filter function	NO
IEC compliance	NO
Insulation resistance	5000000000 Ω
Insulator color	BLACK
insulator material	POLYETHYLENE
JESD-609 code	e0
MIL compliance	NO
Manufacturer's serial number	54242
Plug contact pitch	0.1 inch
Match contact row spacing	0.1 inch
Mixed contacts	NO
Installation option 1	LOCKING
Installation method	STRAIGHT
Installation type	BOARD
Number of connectors	ONE
PCB row number	2
Number of rows loaded	2
Maximum operating temperature	125 °C
Minimum operating temperature	-65 °C
Options	GENERAL PURPOSE
PCB contact pattern	RECTANGULAR
PCB contact row spacing	5.461 mm
Plating thickness	15u inch
Rated current (signal)	3 A
Guideline	UL, CSA
reliability	COMMERCIAL
Terminal pitch	2.54 mm
Termination type	SURFACE MOUNT
Total number of contacts	46
UL Flammability Code	94V-0

PDM: Rev:G

STATUS:

Released

Printed: Jun 13, 2008

Using FPGA to measure time interval with high accuracy: Hello everyone, I would like to ask, has anyone used FPGA to make high-precision time measurements, with time intervals of 0.1ns or 10ps? I have seen literature showing that someone used FPGA to achie...; cqr FPGA/CPLD

[Jihai APM32E103VET6S MINI Development Board Review] Second post PLL and system clock questions: After a quick look at the Polaris data sheet, I have some questions about the PLL clock and system clock.Simply speaking, the maximum output clock of PLL should be 96MHZThe maximum system clock is 120...; 常见泽1 Domestic Chip Exchange

Regarding the issue of changing BMI of xmc1300 chip: Use the JLINK of xmc1300kit to program the port to in this mode and change its BMI. Can any expert explain how to do this?...; wr12306 Power technology

Universal emulation card CNIC-A2PX: Seek the truth, what is this thing?...; 百合2014 Download Centre

Ink screen calendar based on AB32 and RT-Thread, open source: Project Background This project is one of the participating projects in the [RT-Thread x RISC-V Application Innovation Competition] Project Introduction What problem does this project solve?Traditiona...; Fillmore Real-time operating system RTOS

Transistor common emitter amplifier circuit: [i=s]This post was last edited by S3S4S5S6 on 2020-8-25 15:51[/i]The figure below is a basic triode amplifier circuit. The circuit parameters are marked in the figure. C12 is 4.7pF. The other paramete...; S3S4S5S6 Analog electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components