532EB970M000BGR datasheet, PDF

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532EB970M000BGR: DescriptionOscillator; CategoryPassive components oscillator; File Size200KB，10 Pages; ManufacturerSilicon Laboratories Inc

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Si532

R E L I M I N A R Y

A TA

H E E T

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

Two selectable output frequencies

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 6.

Applications

SONET/SDH

Networking

SD/HD video

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 5.

(Top View)

GND

Description

The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced

DSPLL

circuitry to provide a low jitter clock at high frequencies. The Si532 is

available with any-rate output frequency from 10 to 945 MHz and select

frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is

required for each output frequency, the Si532 uses one fixed crystal

frequency to provide a wide range of output frequencies. This IC based

approach allows the crystal resonator to provide exceptional frequency

stability and reliability. In addition, DSPLL clock synthesis provides superior

supply noise rejection, simplifying the task of generating low jitter clocks in

noisy environments typically found in communication systems. The Si532 IC

based XO is factory configurable for a wide variety of user specifications

including frequency, supply voltage, output format, and temperature stability.

Specific configurations are factory programmed at time of shipment, thereby

eliminating long lead times associated with custom oscillators.

CLK–

CLK+

(LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

(CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

Preliminary Rev. 0.4 5/06

Si532

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

Si532

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Supply Voltage

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Supply Current

Output enabled

TriState mode

Output Enable (OE)

Operating Temperature Range

Min

2.97

2.25

1.71

—

0.75 x V

—

–40

Typ

3.3

2.5

1.8

—

Max

3.63

2.75

1.89

—

0.5

Units

ºC

Notes:

Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 6 for further details.

OE pin includes a 17 kΩ pullup resistor to V

. Pulling OE to ground causes outputs to tristate.

Table 2. CLK± Output Frequency Characteristics

Parameter

Nominal Frequency

1,2

Symbol

Test Condition

LVPECL/LVDS/CML

CMOS

Min

—

–20

–50

Typ

—

±1.5

—

Max

945

160

—

+20

+50

±10

Units

MHz

Initial Accuracy

Measured at +25 °C at

time of shipping

ppm

Temperature Stability

1,3

Aging

Powerup Time

Settling Time After FS Change

∆f/f

Frequency drift over

projected 15 year life

OSC

FRQ

—

Notes:

See Section 3. "Ordering Information" on page 6 for further details.

Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

Selectable parameter specified by part number.

Time from powerup or tristate mode to f

Preliminary Rev. 0.4

Si532

Table 3. CLK± Output Levels and Symmetry

Parameter

LVPECL Output Option

Symbol

Test Condition

mid-level

swing (diff)

swing (single-ended)

mid-level

swing (diff)

Min

– 1.42

1.1

0.5

1.125

0.32

Typ

—

Max

– 1.25

1.9

0.93

1.275

0.50

Units

—

1.20

0.40

LVDS Output Option

CML Output Option

mid-level

swing

(diff)

= 32 mA

—

0.70

0.8 x V

– 0.75

0.95

—

1.20

CMOS Output Option

—

0.4

350

—

Rise/Fall time (20/80%)

LVPECL/LVDS/CML

CMOS with CL = 15 pF

Symmetry (duty cycle)

SYM

LVPECL:

LVDS:

CMOS:

– 1.3 V (diff)

1.25 V (diff)

Notes:

Ω

to V

– 2.0 V.

term

= 100

Ω

(differential).

= 15 pF

Table 4. CLK± Output Phase Jitter

Parameter

Phase Jitter (RMS)*

for F

OUT

> 500 MHz

Phase Jitter (RMS)*

for F

OUT

of 125 to 500 MHz

Symbol

Test Condition

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

12 kHz to 20 MHz (OC-48)

Min

—

Typ

0.27

0.30

0.50

Max

—

Units

*Note:

Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.

Table 5. CLK± Output Period Jitter

Parameter

Period Jitter*

for F

OUT

< 160 MHz

Symbol

PER

Test Condition

RMS

Peak-to-Peak

Min

—

Typ

Max

—

Units

*Note:

Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles.

Preliminary Rev. 0.4

Si532

Table 6. CLK± Output Phase Noise (Typical)

Configuration

Output

Offest Frequency (f)

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

10 MHz

100 MHz

–110

–127

–134

–136

–143

–147

n/a

81.25 MHz

LVDS

(f)

–100

–115

–119

–123

–135

–144

–147

–87

–102

–107

–111

–121

–135

–142

312.5 MHz

LVPECL

1066 MHz

LVPECL

Units

dBc/Hz

Table 7. Absolute Maximum Ratings

Parameter

Supply Voltage

Input Voltage (any input pin)

Storage Temperature

ESD Sensitivity (HBM, per JESD22-A114)

Soldering Temperature (Pb-free profile)

Soldering Temperature Time @ T

PEAK

(Pb-free profile)

Symbol

ESD

PEAK

Rating

–0.5 to +3.8

–0.5 to V

+ 0.3

–55 to +125

>2500

260

Units

Volts

ºC

Volts

ºC

seconds

Notes:

Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions.

Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO

for further information, including

soldering profiles.

Table 8. Environmental Compliance

The Si532 meets the following qualification test requirements.

Parameter

Mechanical Shock

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solvents

Conditions/ Test Method

MIL-STD-883F, Method 2002.3 B

MIL-STD-883F, Method 2007.3 A

MIL-STD-883F, Method 203.8

MIL-STD-883F, Method 1014.7

MIL-STD-883F, Method 2016

Preliminary Rev. 0.4

Si532

2. Pin Descriptions

(Top View)

GND

CLK–

CLK+

CLK

LVDS/LVPECL/CML

CMOS

Table 9. Pin Descriptions

Symbol

FS*

LVDS/LVPECL/CML Function

Frequency Select

0 = First frequency selected

1 = Second frequency selected

CMOS Function

Frequency Select

0 = First frequency selected

1 = Second frequency selected

OE*

GND

CLK+

CLK–

Output enable

0 = clock output disabled (outputs tristated) 0 = clock output disabled (outputs tristated)

1 = clock output enabled

Electrical and Case Ground

Oscillator Output

Complementary output

Power Supply Voltage

Electrical and Case Ground

Oscillator Output

No connection

Power Supply Voltage

*Note:

FS and OE include a 17 kΩ pullup resistor to V

. See Section 3. “Ordering Information” for details on frequency value

ordering.

Preliminary Rev. 0.4

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