EEWORLDEEWORLDEEWORLD

Part Number

Search

FP20216152402AKECW

Description
Array/Network Resistor, Bussed, Thin Film, 0.1W, 24000ohm, 100V, 0.05% +/-Tol, -100,100ppm/Cel, 4427,
CategoryPassive components    The resistor   
File Size92KB,3 Pages
ManufacturerVishay
Websitehttp://www.vishay.com
Environmental Compliance
Download Datasheet Parametric View All

FP20216152402AKECW Overview

Array/Network Resistor, Bussed, Thin Film, 0.1W, 24000ohm, 100V, 0.05% +/-Tol, -100,100ppm/Cel, 4427,

FP20216152402AKECW Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid976788664
Reach Compliance Codecompliant
Country Of OriginUSA
ECCN codeEAR99
YTEOL6.9
structureFlatpack
Network TypeBussed
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package height2.03 mm
Package length11.18 mm
Package formDIP
Package width6.73 mm
method of packingWaffle Pack
Rated power dissipation(P)0.1 W
resistance24000 Ω
Resistor typeARRAY/NETWORK RESISTOR
seriesFP202
size code4427
technologyTHIN FILM
Temperature Coefficient100 ppm/°C
Tolerance0.05%
Operating Voltage100 V
FP200, FP201, FP202
www.vishay.com
Vishay Dale Thin Film
Hermetic Flat Pack Thin Film Resistor, Surface Mount Network
FEATURES
Product may not
be to scale
Military/aerospace
Hermetically sealed
Compliant to RoHS Directive 2002/95/EC
Halogen-free according to IEC 61249-2-21
definition
Note
*
Pb containing terminations are not RoHS compliant, exemptions
may apply
Vishay Dale Thin Film offers a broad line of precision resistor
networks in hermetic Flat-Packs for surface mount
requirements in military, space or other harsh environmental
applications. These networks provide the long-term stability
necessary to insure continuous specification and
performance over the 20 years to 30 years life required for
space applications. The fabrication of these devices is
performed under tight procedural and environmental
controls to insure conformance to all 883C level H or K
requirements. Custom configurations, values and tolerance
combinations are available with fast turnaround.
SCHEMATICS
FP200
Number of Resistors
Number of Leads
Type Connection
Values Available
1
7, 8
14, 16
Isolated
500
to 100 k
FP201
Number of Resistors
Number of Leads
Type Connection
Values Available
12, 14
14, 16
Series
500
to 100 k
1
FP202
Number of Resistors
Number of Leads
Type Connection
Values Available
1
13, 15
14, 16
Common
500
to 100 k
STANDARD ELECTRICAL SPECIFICATIONS
TEST
Material
Pin/Lead Number
Resistance Range
TCR: Absolute
TCR: Tracking
Tolerance: Absolute
Tolerance: Ratio
Power Rating: Resistor
Power Rating: Package
Stability: Absolute
Stability: Ratio
Voltage Coefficient
Working Voltage
Operating Temperature Range
Storage Temperature Range
Noise
Thermal EMF
Shelf Life Stability: Absolute
Shelf Life Stability: Ratio
Revision: 20-Oct-11
SPECIFICATIONS
Passivated nichrome
14, 16
10
to 1 M (total)
± 10 ppm/°C to 50 ppm/°C
± 5 ppm/°C (standard)
± 0.05 % to ± 1 %
± 0.01 % to ± 0.1 %
100 mW
800 mW
R
± 0.05 %
R
± 0.015 %
-
100 V max. not to exceed
P
x
R
- 55 °C to + 125 °C
- 55 °C to + 150 °C
-
-
R
± 0.01 %
R
± 0.002 %
CONDITIONS
-
-
-
-
-
-
-
-
70 °C
2000 h at + 70 °C
2000 h at + 70 °C
-
-
-
-
-
-
1 year at + 25 °C
1 year at + 25 °C
Document Number: 61073
1
For technical questions, contact:
thinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
EDA Tools Manual
...
wzt FPGA/CPLD
LM3S8962 Serial Port
I'm trying to debug the serial port but it doesn't work. Can someone tell me what's going on? #include "systemInit.h" #include uart.h // UART initialization void uartInit(void) {SysCtlPeriEnable(SYSCT...
beyondvv Microcontroller MCU
Developers use experiments and data analysis
Developers use experiments and data analysis Open the project in μVision v5: "BLEMLC", compile and generate: "BLEMLC.bin". Use "STM32CubeProgrammer", unplug the battery first, press and hold the "ROOT...
lvqy ST MEMS Sensor Creative Design Competition
Accelerate FPGA design timing closure using graph-based physical synthesis
Traditional synthesis techniques are increasingly unable to meet the needs of today's very large and complex FPGA designs implemented in 90nm and below process nodes. The problem is that traditional F...
songrisi FPGA/CPLD
Reliability Analysis Using Six Sigma Software JMP
Time: 2010-07-05 10:15:35 Source: EEPW Author: Reliability is a problem that exists in every link of product design, manufacturing and use. Simply put, reliability is the degree to which a product is ...
安_然 Test/Measurement
Those who are familiar with fat32 please come in--waiting online
I am currently developing a USB flash drive using K9F2G08X0 flash memory. The flash memory is 256M in size, with a total of 2048 blocks, each with 64 pages. This means each block is 128K. However, the...
hconfeng Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1612  2281  2750  963  277  33  46  56  20  6 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号