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74HC112PW,118

Description
flip flops dual J-K neg edge
Categorylogic    logic   
File Size92KB,16 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74HC112PW,118 Overview

flip flops dual J-K neg edge

74HC112PW,118 Parametric

Parameter NameAttribute value
Brand NameNXP Semiconduc
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeTSSOP
package instructionPLASTIC, SOT-403-1, TSSOP-16
Contacts16
Manufacturer packaging codeSOT403-1
Reach Compliance Codeunknow
seriesHC/UH
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-K FLIP-FLOP
Humidity sensitivity level1
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)265 ns
Certification statusNot Qualified
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)4.5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNICKEL PALLADIUM GOLD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typeNEGATIVE EDGE
width4.4 mm
minfmax24 MHz
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT112
Dual JK flip-flop with set and reset;
negative-edge trigger
Product specification
Supersedes data of December 1990
File under Integrated Circuits, IC06
1998 Jun 10

74HC112PW,118 Related Products

74HC112PW,118 74HCT112D,652 74HCT112DB,118
Description flip flops dual J-K neg edge flip flops dual JK F/F neg-edge flip flops dual J-K neg edge
Brand Name NXP Semiconduc NXP Semiconduc NXP Semiconduc
Is it Rohs certified? conform to conform to conform to
Maker NXP NXP NXP
Parts packaging code TSSOP SOP SSOP1
package instruction PLASTIC, SOT-403-1, TSSOP-16 PLASTIC, SOT-109-1, SO-16 SSOP,
Contacts 16 16 16
Manufacturer packaging code SOT403-1 SOT109-1 SOT338-1
Reach Compliance Code unknow compli unknow
series HC/UH HCT HCT
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
JESD-609 code e4 e4 e4
length 5 mm 9.9 mm 6.2 mm
Load capacitance (CL) 50 pF 50 pF 50 pF
Logic integrated circuit type J-K FLIP-FLOP J-K FLIP-FLOP J-K FLIP-FLOP
Humidity sensitivity level 1 1 1
Number of digits 2 2 2
Number of functions 2 2 2
Number of terminals 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260
propagation delay (tpd) 265 ns 60 ns 60 ns
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.1 mm 1.75 mm 2 mm
Maximum supply voltage (Vsup) 6 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) 2 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) 4.5 V 5 V 5 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD NICKEL PALLADIUM GOLD
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 1.27 mm 0.65 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
width 4.4 mm 3.9 mm 5.3 mm
minfmax 24 MHz 20 MHz 20 MHz
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