Supertex inc.
High-Voltage,
Current-Mode PWM Controller
Features
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10 to 450V input voltage range
<1.3mA supply current
>1.0MHz clock
>20:1 dynamic range @ 500KHz
49% Maximum duty cycle version
Low internal noise
HV9120
Applications
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Off-line high frequency power supplies
Universal input power supplies
High density power supplies
Very high efficiency power supplies
Extra wide load range power supplies
General Description
The Supertex HV9120 is a Switch Mode Power Supply
(SMPS) controller subsystem that can start and run directly
from almost any DC input, from a 12V battery to a rectified
and filtered 240V AC line. It contains all the elements
required to build a single-switch converter except for the
switch, magnetic assembly, output rectifier(s) and filter(s).
A unique input circuit allows the HV9120 to self-start directly
from a high voltage input, and subsequently take the power
to operate from one of the outputs of the converter it is
controlling, allowing very efficient operation while maintaining
input-to-output galvanic isolation limited in voltage only by
the insulation system of the associated magnetic assembly.
A ±2% internal bandgap reference, internal operational
amplifier, very high speed comparator, and output buffer
allow production of rugged, high performance, high efficiency
power supplies of 50W or more, which can still be over 80%
efficient at outputs of 1.0W or less. The wide dynamic range of
the controller system allows designs with extremely wide line
and load variations with much less difficulty and much higher
efficiency than usual. The exceptionally wide input voltage
range also allows better usage of energy stored in input
dropout capacitors than with other PWM ICs. Remote on/off
controls allow either latching or nonlatching remote shutdown.
During shutdown, the power required is under 6.0mW.
For detailed circuit and application information, please
refer to application notes AN-H13, AN-H21 to AN-H24.
Functional Block Diagram
15
FB
(19)
COMP
14 (18)
Error
Amplifier
11 (14)
VREF
REF
GEN
–
+
4V
2V
–
+
+
–
16 (20)
BIAS
7 (9)
VDD
1 (3)
+VIN
Current
Sources
1.2V
To
Internal
Circuits
–
–
+
8.1V
8.6V
+
Undervoltage
Comparator
S
R
Current Limit
Comparator
OSC
OSC
IN
OUT
9 (11) 8 (10)
OSC
Modulator
Comparator
T
R
S
Q
Q
To VDD
5 (6)
OUTPUT
6 (8)
-VIN
V
DD
4 (5)
SENSE
12 (16)
SHUTDOWN
13 (17)
RESET
Q
Pre-regulator/Startup
Note:
Pin numbers in parentheses are for PLCC package.
Doc.# DSFP-HV9120
B060412
Supertex inc.
www.supertex.com
HV9120
Ordering Information
Part Number
HV9120NG-G
HV9120NG-G M934
HV9120P-G
HV9120PJ-G
HV9120PJ-G M910
Package Options
16-Lead SOIC
16-Lead SOIC
16-Lead PDIP
20-Lead PLCC*
20-Lead PLCC*
Packing
45/Tube
2500/Reel
24/Tube
48/Tube
1000/Reel
16-Lead SOIC (NG)
2
1
20
Pin Configurations
1
16
1
16
4
16-Lead PDIP (P)
-G Indicates package is RoHS compliant (‘Green’)
*
Obsolescence notice issued for the product in the 20-Lead PLCC package.
Typical Thermal Resistance
Package
16-Lead SOIC
16-Lead PDIP
20-Lead PLCC
θ
ja
83
O
C/W
51
O
C/W
66
O
C/W
20-Lead PLCC (PJ)
Product Marking
Top Marking
YWW
HV9120NG
LLLLLLLL
Bottom Marking
Absolute Maximum Ratings
Parameter
Input voltage, +V
IN
Device supply voltage, V
DD
Logic input voltage
Linear input voltage
Pre regulator input current
(continuous), I
IN
Operating junction temperature, T
J
Storage temperature
Power dissipation:
16-Lead SOIC
16-Lead PDIP
20-Lead PLCC
900mW
1000mW
1400mW
Value
450V
15.5V
-0.3V to V
DD
+0.3V
-0.3V to V
DD
+0.3V
2.5mA
150
O
C
-65 to +150
O
C
CCCCCCCCC AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
16-Lead SOIC (NG)
Top Marking
H V9 120 P
YYWW
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
16-Lead PDIP (P)
Top Marking
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Voltages
are referenced to -V
IN
.
YY = Year Sealed
WW = Week Sealed
HV9120PJ
LLLLLLLLLL
L = Lot Number
A = Assembler ID
Bottom Marking
C = Country of Origin*
= “Green” Packaging
YYWW AAA
CCCCCCCCCCC
*May be part of top marking
Package may or may not include the following marks: Si or
20-Lead PLCC (PJ)
Doc.# DSFP-HV9120
B060412
2
Supertex inc.
www.supertex.com
HV9120
Test Circuits
+10V
(V
DD
)
Error Amp Z
OUT
1.0V swept 100Hz - 2.2MHz
0.1V swept 10Hz - 1.0MHz
PSRR
100K 1%
(FB)
60.4K
–
+
10.0V
100K1%
4.0V
–
+
Reference
GND
(-V
IN
)
0.1µF
V
1
Tektronix
P6021
(1 turn
secondary)
V
1
V
2
40.2K
V
2
Reference
0.1µF
Note:
Set feedback voltage so that V
COMP
= V
DIVIDE
± 1.0mV before connecting transformer.
Detailed Description
The pre regulator/startup circuit for the HV9120 consists of
a high-voltage n-channel depletion-mode DMOS transistor
driven by an error amplifier to form a variable current path
between the VIN terminal and the VDD terminal. Maximum
current (about 20 mA) occurs when V
DD
= 0, with current re-
ducing as V
DD
rises. This path shuts off altogether when V
DD
rises to somewhere between 7.8 and 9.4V, so that if V
DD
is
held at 10 or 12V by an external source (generally the sup-
ply the chip is controlling), no current other than leakage is
drawn through the high voltage transistor. This minimizes
dissipation.
An external capacitor between VDD and VSS is generally
required to store energy used by the chip in the time be-
tween shutoff of the high voltage path and the VDD supply’s
output rising enough to take over powering the chip. This
capacitor should have a value of 100X or more the effective
gate capacitance of the MOSFET being driven, i.e.,
C
STORAGE
≥ 100 x (gate charge of FET at 10V)
as well as very good high frequency characteristics. Stacked
polyester or ceramic caps work well. Electrolytic capacitors
are generally not suitable. A common resistor divider string
is used to monitor V
DD
for both the undervoltage lockout cir-
cuit and the shutoff circuit of the high voltage FET. Setting
the undervoltage sense point about 0.6V lower on the string
than the FET shutoff point guarantees that the undervoltage
lockout always releases before the FET shuts off.
Pre regulator
V
DD
is used, or a 510 to 680KΩ resistor if V
DD
will be 12V. A
precision resistor is not required; ±5% is fine.
The clock oscillator of the HV9120 consists of a ring of
CMOS inverters, timing capacitors, a capacitor discharge
FET, and a frequency dividing flip-flop. A single external re-
sistor between the OSC IN and OSC OUT pins is required
to set oscillator frequency (see graph).
One difference exists between the Supertex HV9120 and
competitive 9120s: The oscillator is shut off when a shutoff
command is received. This saves about 150µA of quiescent
current, which aids in the construction of power supplies
to meet CCITT specification I-430, and in other situations
where an absolute minimum of quiescent power dissipation
is required.
Clock Oscillator
Reference
The Reference of the HV9120 consists of a stable bandgap
reference followed by a buffer amplifier which scales the
voltage up to approximately 4.0V. The scaling resistors of
the reference buffer amplifier are trimmed during manufac-
ture so that the output of the error amplifier, when connected
in a gain of -1 configuration, is as close to 4.0V as possible.
This nulls out any input offset of the error amplifier. As a con-
sequence, even though the observed reference voltage of a
specific part may not be exactly 4.0V, the feedback voltage
required for proper regulation will be.
A ≈ 50KΩ resistor is placed internally between the output
of the reference buffer amplifier and the circuitry it feeds
(reference output pin and non-inverting input to the error
amplifier). This allows overriding the internal reference with
a low-impedance voltage source ≤6.0V. Using an external
reference reinstates the input offset voltage of the error am-
plifier, and its effect of the exact value of feedback voltage
5
Bias Circuit
An external bias resistor, connected between the bias pin
and VSS is required by the HV9120 to set currents in a se-
ries of current mirrors used by the analog sections of the
chip. Nominal external bias current requirement is 15 to
20µA, which can be set by a 390 to 510KΩ resistor if a 10V
Doc.# DSFP-HV9120
B060412
Supertex inc.
www.supertex.com
FPGA/CPLD
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