EVALUATION KIT AVAILABLE
DS3923
High-Speed Current Mirror
with Sample/Hold Output
General Description
The DS3923 high-speed current mirror integrates high-
voltage devices necessary for monitoring the burst-mode
receive power signal in avalanche photodiode (APD) bias-
ing and optical line terminal (OLT) applications. It provides
small and large gain current mirror outputs to monitor the
APD current. A sample/hold circuit with automatic gain
selection captures the sampled signal so that an external
ADC can accurately measure the signal. An adjustable
current clamp limits current through the APD. The clamp
also features an external shutdown. An integrated FET
is also provided which can be used to quickly clamp the
high-voltage bias to ground in the case of high optical
input power.
The DS3923 is available in a 24-pin TQFN package and
operates over an extended temperature range of -40°C
to +95°C.
Benefits and Features
●
Accurate Burst-Mode RSSI Measurement with Two
Current Mirror Outputs Improves Dynamic Range
• -32dBm to -5dBm Optical Input Range
• ±0.5dB Accuracy
• Sampling Period as Short as 300ns
• Pin Discharge Option
●
Low-Noise APD Bias with Shutdown Options
Reduces Receiver Sensitivity
• 15V to 76V APD Bias
• External Capacitor Connection for Controlled RC
Time Constant of APD Voltage Filter
• Current Clamp with Adjustable Limit and External
Shutdown with Limit Status
• High-Voltage Switch FET for APD Fast Shutdown
●
Small Package Reduces Total Solution Size and Cost
• 3.5mm x 3.5mm, 24-Pin TQFN Package with
Exposed Pad
For related parts and recommended products to use with this part, refer
to
www.maximintegrated.com/DS3923.related.
Applications
●
APD Monitoring
●
GPON OLT
●
10GPON OLT
Ordering Information
appears at end of data sheet.
Typical Application Circuit
R1
100Ω
BOOST
DC-DC
SHDN
VREF
C1
0.1µF
ADJUSTED FROM 55V AT -40°C TO 65V AT 95°C
C2
0.1µF
R2
330kΩ
MIRIN
R3
4.99kΩ
ILIMS
3
GAIN
SENXOR
ISRC/
SHDN
30kΩ
>300ns PULSE
OCCURS ONCE PER
100µS TO ONCE
PER 100ms
300ns
min
3.3V
0V
250µw
1µw
PAPD
3.3V
3.3V
AVCC
VCC
1.8V
GND
MIRIN
SEN
MIROUT
APD
C3
330pF
TO
500pF
APDV
VIP1
R4
1kΩ
C4
OPT.
VIP2
R5
1kΩ
C5
OPT.
10µA
ISRC
I1
HVD
HVG
DS3923
GPIO
DAC
GPIO
0.8I1
0.2I1
0.1I1
IOUT
R6
APD SHUTDOWN
GPIO[2:0]
GPIO
CURRENT
LIMIT
TEMP
LIMIT
RLIM
3.3V
DISCHARGE
DUAL
GAIN
SAMPLE/
HOLD
VOP
VON
VIN
DIFFEN
R7
DS4830A
CLD
GPIO
0V
(EDGE INTERRUPT)
[DETECT SEN EDGE] 250µw
ADC [BM RSSI MONITOR,
AVERAGE RSSI,
MIRROR VOLTAGE DROP
DC-DC FEEDBACK]
TIA
4
19-6848; Rev 2; 3/15
DS3923
High-Speed Current Mirror
with Sample/Hold Output
Absolute Maximum Ratings
Voltage on HVD, MIRIN, MIRCAP, and MIROUT
Relative to HVGND ..........................................-0.3V to +79V
Voltage on V
CC
and AVCC to GND ....................-0.3V to + 4.3V
Voltage on All Other Pins Relative
to GND...................-0.3V to (V
CC
+ 0.3V) Not to Exceed +4V
Continuous Power Dissipation (T
A
= +70°C)
TQFN (derate 15.4mW/°C above +70°C)...............1228.9mW
Storage Temperature Range ............................ -65°C to +150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
MIRIN
= 15V to 76V, V
CC
= 2.85V to 3.63V, T
A
= -40°C to +95°C, unless otherwise noted.) (Note 1)
PARAMETER
Low Voltage Supply
Low Voltage Current
MIRIN Quiescent Current
MIRIN Voltage
HV FET On-Resistance
HVG Voltage
HVD Voltage
HVD Leakage
Logic-Input Thresholds (DIFFEN,
DISCHARGE, GAIN, HVG, SEN,
SENXOR)
SYMBOL
V
CC
I
CC
I
MIRIN
V
MIRIN
R
DSONHV
V
GSHV
V
DHV
I
ILHV
V
IL
V
IH
V
IL_SHDN
ISRC/SHDN Threshold
ISRC/SHDN Resistor
Maximum MIROUT Current
V
IH_SHDN
R
ISRC
I
CLAMP
(Note 3
ISRC/SHDN =
low
R
LIM
=
40.2kΩ
R
LIM
=
24.9kΩ
V
CC
-
0.2
CONDITIONS
(Note 2)
V
MIRIN
= 60V,
ISRC/SHDN =
30kΩ to GND
I
MIROUT
= 0µA
I
MIROUT
= 1mA
MIN
2.85
TYP
8
1
3.2
MAX
3.63
16
2
4
76
2
V
CC
+
0.3
76
+1
0.3 x
V
CC
UNITS
V
mA
mA
V
Ω
V
V
µA
15
V
GS
= 3.0V, I
D
= 170mA
0
0.85
-1
0.7 x
V
CC
1.4
V
V
30
2
3.2
30.3
2.8
4.1
0.01
mA
kΩ
29.7
1.4
2.5
ISRC/SHDN = high
MIROUT Capacitive Load
C
MIROUT
V
OL_ILIMS
Logic Output Levels (ILIMS)
V
OH_ILIMS
I
ILIMS
= +2mA
Total capacitance on MIROUT to
achieve accuracy specification
I
ILIMS
= -2mA
V
CC
-0.45
330
500
0.45
pF
V
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Maxim Integrated
│
2
DS3923
High-Speed Current Mirror
with Sample/Hold Output
Electrical Characteristics (continued)
(V
MIRIN
= 15V to 76V, V
CC
= 2.85V to 3.63V, T
A
= -40°C to +95°C, unless otherwise noted.) (Note 1)
PARAMETER
Logic Output Levels (GAIN Has
3.5kΩ Internal Nominal Impedance)
ILIMS
Output Time
IOUT to MIROUT Ratio
VIP1 to MIROUT Ratio
VIP2 to MIROUT Ratio
K
VIP1
, K
VIP2
, and K
IOUT
Voltage
Variation
Mirror Voltage Drop Monitor Load
Capacitance
Mirror Voltage Drop
Shutdown Temperature
Shutdown Temperature Hysteresis
VIP1 Offset Current
VIP2 Offset Current
IOUT Offset Current
SYMBOL
V
OL
V
OH
t
ILIMS
K
IOUT
K
VIP1
K
VIP2
K
VAR
V
APDV:CAP
V
MIRIN
-
V
MIROUT
T
SHDN
T
HYS
I
VIP1OFF
I
VIP2OFF
I
OUTOFF
R
ISRC
= 30kΩ
R
ISRC
= 30kΩ
R
ISRC
= 30kΩ
CONDITIONS
I
GAIN
= -30µA
I
GAIN
= +30µA
(Note 4)
I
MIROUT
= 1mA
I
MIROUT
= 1mA
I
MIROUT
= 1mA
V
MIRIN
= 40V ± 10%
External capacitance required on
APDV
Current limit not exceeded,
V
SHDN
= Hi-Z, I
MIRIN
= 1mA
50
4
150
20
20
19
18
40
30
25
0.090
0.720
0.180
V
CC
-
0.4
1
0.100
0.800
0.200
±0.3
0.110
0.880
0.220
±2.5
250
MIN
TYP
MAX
0.4
V
µs
A/A
A/A
A/A
%
pF
V
°C
°C
µA
µA
µA
UNITS
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Maxim Integrated
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3
DS3923
High-Speed Current Mirror
with Sample/Hold Output
Sample and Hold Parameters
(V
MIRIN
= 15V to 76V, V
CC
= 2.85V to 3.63V, T
A
= -40°C to +95°C, R
ISRC
= 30kΩ, DISCHARGE = high, unless otherwise noted.)
(Note 1)
PARAMETER
Output Error (Total Error from All
Sources)
SYMBOL
CONDITIONS
I
MIROUT
from 600µA to 60uA
(Note 5)
I
MIROUT
from 20µA to 500µA
(Note 5)
V
OUT
= V
VOP
- V
VON
,
100kΩ output load
V
DIFFEN
= High
Capacitance for stable operation
320
(Note 6)
1kΩ resistors connected to VIP1
and VIP2 (Note 7)
(Note 7)
Less than 1% change from the
time the output is valid, C
LD
=
50pF (Notes 7 and 8)
2.1
300
10
9
109
400
3.5
-9.0
0
1.4
1
50
460
4.9
MIN
TYP
±5.5
%
+9.0
2.5
V
V
kΩ
pF
mV
kΩ
ns
ns
µs
MAX
UNITS
V
ERR
Output Voltage
Output Voltage Common Mode
Output Impedance
VOP Output Capacitive Load
Gain Selection Threshold
GAIN Impedance
Sample Time
Delay Time
Output Valid Time
V
OUT
V
OUTCM
R
OUT
C
LD
V
GTHR
R
G
t
S
t
DEL
t
O_VAL
Note 1: Limits are 100% tested at T
A
= +25°C. Limits over the operating temperature range and relevant supply voltage rating are
guaranteed by design and characterization.
Note 2: ISRC/SHDN is not connected; HV FET is driven by a 100Ω source at 250kHz with a 2.97V square wave; HVD is connected
to GND.
Note 3: External resistor connected to GND. This value guarantees accuracy of DS3923. I
ISRC
= (6/R
ISRC
) ±6%.
Note 4: Resistor connected to RLIM for 1mA clamp limit. I
MIROUT
step from 10μA to 10mA. Time measured from I
MIROUT
step to
I
MIROUT
< 1.1mA (see the
Typical Application Circuit).
C3 = 47pF, C1 = C2 = 0.1μF, V
VC1
= 30V; R1 = 100Ω.
Note 5: Output Error = VOP – 4 x (VIP1 or VIP2) and sampled at t
OUT
. Measured at +25°C with offset removed.
Note 6: To change internal gain selection, external driver must be capable of meeting the GAIN input logic level with the GAIN
impedance connected to either V
CC
or GND.
Note 7: See Figure 1 for more detail on timing.
Note 8: Time referenced to SENINT falling edge when output is valid at VOP - VON if DIFFEN = High or VOP if DIFFEN = Low.
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Maxim Integrated
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4
DS3923
High-Speed Current Mirror
with Sample/Hold Output
VIP1/VIP2
t
S
t
DEL
SENINT
t
O_VAL
MIN
t
O_VAL MAX
OUTPUT VALID
VOP - VON
VOLTAGE INVALID
GAIN
GAIN VALID
GAIN VALID
t
ADC
EXTERNAL
ADC DATA
t
S
= SAMPLE TIME
t
DEL
= DELAY TIME
t
ADC
= ADC CONVERSION TIME
DATA VALID
t
O_VAL
= OUTPUT VALID TIME
UL
VOP - VON
LL
LOWER LIMIT (LL)
VIP1 < 0.4
VIP1 > = 0.4
(0.91 x 4 x IM x R
VIP1
)/1.25
(0.91 x 4 x IM x R
VIP2
)/5
UPPER LIMIT (UL)
(1.09 x 4 x IM x R
VIP1
)/1.25
(1.09 x 4 x IM x R
VIP2
)/5
IM = MIRROR CURRENT
R
VIP1
: RESISTOR BETWEEN VIP1 TO GROUND
R
VIP2
: RESISTOR BETWEEN VIP2 TO GROUND
Figure 1. DS3923 Sample/Hold Timing Diagram
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