74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 04 — 14 May 2009
Product data sheet
1. General description
The 74LV574 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop
and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output
enable (OE) input are common to all flip-flops. It is a low-voltage Si-gate CMOS device
and is pin and functionally compatible with the 74HC574 and 74HCT574.
The eight flip-flops will store the state of their individual D-inputs that meet the set-up and
hold times requirements on the LOW to HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE
is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does
not affect the state of the flip-flops.
2. Features
I
I
I
I
I
I
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
°C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
°C
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
Common 3-state output enable input
Multiple package options
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
I
I
I
3. Ordering information
Table 1.
Type
number
74LV574N
74LV574D
74LV574DB
Ordering information
Package
Temperature range
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
DIP20
SO20
SSOP20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads; body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
Version
SOT146-1
SOT163-1
SOT339-1
SOT360-1
74LV574PW
−40 °C
to +125
°C
TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
NXP Semiconductors
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
4. Functional diagram
11
1
11
2
3
4
5
6
7
8
9
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna798
C1
EN
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
8
9
3
4
5
6
7
1D
19
18
17
16
15
14
13
12
mna446
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0 19
Q1 18
Q2 17
Q3 16
Q4 15
Q5 14
Q6 13
Q7 12
11 CP
1 OE
mna800
Fig 3.
Functional diagram
74LV574_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 May 2009
2 of 17
NXP Semiconductors
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna801
Fig 4.
Logic diagram
5. Pinning information
5.1 Pinning
74LV574
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
001aaj968
74LV574
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
001aaj969
GND 10
GND 10
Fig 5.
Pin configuration DIP20, SO20
Fig 6.
Pin configuration SSOP20, TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
D0 to D7
GND
CP
Q0 to Q7
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
output enable input (active LOW)
data input
ground (0 V)
clock input (LOW to HIGH; edge triggered)
data output
supply voltage
74LV574_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 May 2009
3 of 17
NXP Semiconductors
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable
outputs
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑
= LOW to HIGH clock transition
Operating mode
Internal flip-flop Output
CP
↑
↑
↑
↑
Dn
l
h
l
h
L
H
L
H
Qn
L
H
Z
Z
L
L
H
H
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
=
−40 °C
to +125
°C
DIP20
SO20, SSOP20 and TSSOP20
[1]
[2]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Min
−0.5
-
-
-
-
−70
−65
-
-
Max
+7.0
±20
±50
±35
70
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP20 packages: above 70
°C
the value of P
tot
derates linearly with 12 mW/K.
For SO20 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
74LV574_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 May 2009
4 of 17
NXP Semiconductors
74LV574
Octal D-type flip-flop; positive edge-trigger; 3-state
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
T
amb
∆t/∆V
Parameter
supply voltage
[1]
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.0 V to 2.0 V
V
CC
= 2.0 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 3.6 V to 5.5 V
[1]
Conditions
Min
1.0
0
0
−40
-
-
-
-
Typ
3.3
-
-
+25
-
-
-
-
Max
5.5
V
CC
V
CC
+125
500
200
100
50
Unit
V
V
V
°C
ns/V
ns/V
ns/V
ns/V
The static characteristics are guaranteed from V
CC
= 1.2 V to V
CC
= 5.5 V, but LV devices are guaranteed to function down to
V
CC
= 1.0 V (with input levels GND or V
CC
).
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input voltage
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA;
V
CC
= 1.2 V
I
O
=
−100 µA;
V
CC
= 2.0 V
I
O
=
−100 µA;
V
CC
= 2.7 V
I
O
=
−100 µA;
V
CC
= 3.0 V
I
O
=
−100 µA;
V
CC
= 4.5 V
I
O
=
−8
mA; V
CC
= 3.0 V
I
O
=
−16
mA; V
CC
= 4.5 V
-
1.8
2.5
2.8
4.3
2.4
3.6
1.2
2.0
2.7
3.0
4.5
2.82
4.2
-
-
-
-
-
-
-
-
1.8
2.5
2.8
4.3
2.2
3.5
-
-
-
-
-
-
-
V
V
V
V
V
V
V
−40 °C
to +85
°C
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
0.3V
CC
−40 °C
to +125
°C
Unit
Min
0.9
1.4
2.0
0.7V
CC
-
-
-
-
Max
-
-
-
-
0.3
0.6
0.8
V
V
V
V
V
V
V
0.3V
CC
V
74LV574_4
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 May 2009
5 of 17
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