ICS601-01
L
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P
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N
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C
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M
ULTIPLIER
Description
The ICS601-01 is a low-cost, low phase noise,
high-performance clock synthesizer for applications
which require low phase noise and low jitter. It is ICS’
lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using ICS’ patented
analong and digital Phase-Locked Loop (PLL)
techniques, the chip accepts a 10 - 27 MHz crystal or
clock input, and produces output clocks up to 156 MHz
at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input
and output skew and jitter are not defined nor
guaranteed. For applications which require definted
input to output timing, use the ICS670-01.
Features
•
•
•
•
•
•
•
•
Packaged in 16-pin SOIC or TSSOP
Available in Pb (lead) free package
Uses fundamental 10 - 27 MHz crystal or clock
Patented PLL with the lowest phase noise
Output clocks up to 156 MHz at 3.3 V
Low phase noise: -132 dBc/Hz at 10 kHz
Low jitter - 18 ps one sigma typ.
Full swing CMOS outputs with 25 mA drive capability
at TTL levels
•
Advanced, low power, sub-micron CMOS process
•
Industrial temperature range available
•
Operating voltage of 3.3V or 5V
Block Diagram
VDD
3
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
X1/ICLK
Crystal or
clock input
Crystal
Oscillator
X2
ROM Based
Multipliers
REFOUT
VCO
Divide
4
S3:0
3
GND
OE
REFEN
MDS 601-01 L
I n t e gra te d C i r c u i t S y s t e m s
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1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 111204
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS601-01
L
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P
HASE
N
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C
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M
ULTIPLIER
Pin Assignment
CLK
REFEN
VDD
VDD
VDD
X2
S1
X1/ICLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
GND
REFOUT
OE
S0
S3
S2
Multiplier Select Table
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK (see note 2 on following page)
TEST
TEST
Input x1
Input x3
Input x4
Input x5
Input x6
Input x8
TEST
Crystal osc. pass through (no PLL)
Input x2
TEST
Input x8
Input x10
Input x12
Input x16
16 Pin (150 mil) TSSOP or SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14 - 16
Pin
Name
CLK
REFEN
VDD
VDD
VDD
X2
S1
X1/ICLK
S2
S3
S0
OE
REFOUT
GND
Pin
Type
Output
Input
Power
Power
Power
XO
Input
XI
Input
Input
Input
Input
Output
Power
0 = connect directly to ground
1 = connect directly to VDD
Pin Description
Clock output from VCO. Output frequency equals the input frequency times multiplier.
Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Connect to +3.3V or +5V. Must match other VDDs.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Leave disconnected for an external clock input.
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states both output clocks when low. Internal pull-up.
Buffered crystal oscillator clock output. Controlled by REFIN.
Connect to ground.
MDS 601-01 L
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111204
tel (4 08) 297-1 201
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w w w. i c s t . c o m
ICS601-01
L
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P
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N
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C
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M
ULTIPLIER
Achieving Low Phase Noise
Figure 1 shows a typical phase noise measurement in a 125 MHz system. Therea are a few simple steps
that can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will
increase the hase noise, so it is important to have a stable, low noise supply voltage at the device. Use
decoupling capacitors of 0.1µF in parallel with 0.01µF. It is important to have these capacitors as close as
possible to the ICS601-01 supply pins.
Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this
can reduce the phase noise by as much as 10 dBc/Hz.
0
-20
Phase Noise (dBc/Hz)
-40
-60
-80
-100
-120
-140
1.00E
+01
1.00E
+02
1.00E
+03
1.00E
+04
1.00E
+05
1.00E
+06
1.00E+07
O
ffset fromC
arrier (H
z)
Figure 1. Phase N of IC
oise
S601-01 for 125 M z output, 25 M z crystal input.
H
H
VD =3.3 V, R UTdisabled.
D
EFO
External Component/Crystal Selection
The ICS601-01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF and 0.1µF should be connected between VDD and GND, as close to the part as
possible. A series termination resistor of 33Ω may be used for each clock output. The crystal must be
connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do
not use third overtone. For exact tuning when using a crystal, capacitors should beconnected from pins X1
to ground and X2 to ground. In general, the value of these capacitors is given by the following equation,
where CL is the crystal load capacitance: Crystal caps (pF) = (CL - 5) x 2. So for a crystal with 16 pF load
capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board
capacitance and recommend the exact capacitance value to use.
MDS 601-01 L
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS601-01
L
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P
HASE
N
OISE
C
LOCK
M
ULTIPLIER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial version
Ambient Operating Temperature, Industrial version
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70
°C
-40 to +85
°C
-65 to +150
°C
125
°C
260
°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
Max.
+85
+5.5
Units
°C
V
DC Electrical Characteristics
VDD=3.3 V ±10%
, Ambient temperature -40 to +85°C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
Conditions
X1/ICLK pin only
Note 1
X1/ICLK pin only
Note 1
Min.
3.0
VDD/2+1
Typ.
Max.
5.5
Units
V
V
VDD/2-1
2
0.8
V
V
V
V
CMOS level
I
OH
= -4mA
I
OH
= -12mA
I
OL
= 12mA
VDD-0.4
2.4
0.4
Output Low Voltage
V
OL
V
MDS 601-01 L
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS601-01
L
OW
P
HASE
N
OISE
C
LOCK
M
ULTIPLIER
Parameter
Operating Supply Current
Short Circuit Current
Input Capacitance
Symbol
IDD
C
IN
Conditions
No load, 125 MHz
Each output
OE, select pins
Min.
±40
Typ.
22
±60
5
Max.
30
Units
mA
mA
pF
Note 1: Switching occurs nominally at VDD/2
AC Electrical Characteristics
VDD = 3.3V ±10%
, Ambient Temperature -40 to +85° C
Parameter
Input Frequency
Output Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Absolute jitter, short
term, 125 MHz
Maximum jitter, one sigma,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
t
OR
t
OF
Symbol
Fin
Conditions
at 3.3V or 5V
0.8 to 2.0V no load
0.8 to 2.0V, no load
at VDD/2
No load
No load
100 Hz offset
1 kHz
10 kHz offset
100 kHz offset
Min.
10
Typ.
Max.
27
156
1.5
1.5
Units
MHz
MHz
ns
ns
%
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
45
50
±50
12
55
±75
20
-90
-116
-118
-115
-94
-120
-122
-119
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x,
maximum input frequency is 13.75 MHz).
MDS 601-01 L
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 111204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
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