The information given in this document are as a guideline only. We reserve the right to modify our products in any way we deem necessary. Any duplication is prohibited, unless approved in writing.
E13/B
Shell Plating
1
= Bright Tin / Nickel
2
= Nickel
Contact Plating
0
1
2
3
4
=
=
=
=
=
Flash Fold
0.4µm (15µ") Gold
0.76µm (30µ") Gold
Full Flash Gold
1.27µ” (50µ") Gold
Bottom Connector
1
2
3
4
5
6
7
8
9
K
D
E
F
G
M
N
P
Q
R
S
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
9 Pos. Male
9 Pos. Female
15 Pos. Male
15 Pos. Female
25 Pos. Male
25 Pos. Female
15 Pos. High Density Female
50 Pos. Female SCSI
26 Pos. High Density Female
15 Pos. High Density Male
37 Pos. Male
37 Pos. Female
44 Pos. High Density Male
44 Pos. High Density Female
62 Pos. High Density Male
62 Pos. High Density Female
78 Pos. High Density Male
78 Pos. High Density Female
9 Pos. Male + 9 Pos. Male
9 Pos. Female + 9 Pos. Female
For special request, please consult factory
Do not hesitate to contact us for further information
I saw that some pins of the FPGA's jtag interface need to be connected to pull-up resistors. Do the CPLD's jtag interface also need to be connected to pull-up resistors? I use EPM570......
The PCB is smaller than expected. The plan was to place the interfaces on both sides. In the actual layout, it was found that the interfaces do not take up much space and can be placed on the right si...
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 20:00[/i] [b][font=宋体][size=10.5pt]Time[/size][/font][/b][font=宋体][size=10.5pt]: May 6-8, 2008[/size][/font] [b][font=宋体][size=10.5pt]Loca...
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FPGA/CPLD
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