FT24C128A-UMG-B datasheet, PDF

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FT24C128A-UMG-B: DescriptionEEPROM, 128KX8, Serial, CMOS, PDSO8, MSOP-8; Categorystorage storage; File Size235KB，15 Pages; ManufacturerFremont Micro Devices USA; Environmental Compliance

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FT24C128A-UMG-B Overview

EEPROM, 128KX8, Serial, CMOS, PDSO8, MSOP-8

FT24C128A-UMG-B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	8348680945
package instruction	TSSOP,
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	ALSO OPERATES AT 400KHZ AT 1.8V MIN SUPPLY
Maximum clock frequency (fCLK)	1 MHz
JESD-30 code	S-PDSO-G8
length	3 mm
memory density	1048576 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	1.1 mm
Serial bus type	I2C
Maximum supply voltage (Vsup)	5 V
Minimum supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3 mm
Maximum write cycle time (tWC)	5 ms

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24C128A, 24C256A

Two-Wire Serial EEPROM

128K, 256K (8-bit wide)

FEATURES

Low voltage and low power operations:

•

FT24C128A/256A:

= 1.8V to 5.5V

Maximum Standby current < 1µA (typically 0.02µA and 0.06µA

1.8V and 5.5V respectively).

64 bytes page write mode.

Partial page write operation allowed.

Internally organized: 16,384

×8

(128K), 32,768

×8

(256K).

Standard 2-wire bi-directional serial interface.

Schmitt trigger, filtered inputs for noise protection.

Self-timed write cycle (5ms maximum).

1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) Compatibility.

Automatic erase before write operation.

Write protect pin for hardware data protection.

High reliability: typically 1,000,000 cycles endurance.

100 years data retention.

Industrial temperature range (-40

C to 85

C).

Standard 8-pin DIP/SOP/TSSOP/MSOP Pb-free packages.

DESCRIPTION

The FT24C128A/256A series are 131,072/262,144 bits of serial Electrical Erasable and Programmable Read Only

Memory, commonly known as EEPROM. They are organized as 16,384/32,768 words of 8 bits (one byte) each. The

devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These

devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead TSSOP and 8-lead MSOP packages. A standard 2-

wire serial interface is used to address all read and write functions. Our extended V

range (1.8V to 5.5V) devices

enables wide spectrum of applications.

PIN CONFIGURATION

Pin Name

A2, A1, A0

SDA

SCL

Pin Function

Device Address Inputs

Serial Data Input / Open Drain Output

Serial Clock Input

Write Protect

No-Connect

DS3007J-page1

24C128A,24C256A

PIN DESCRIPTIONS

(A) SERIAL CLOCK (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to

clock data out of the EEPROM device.

(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)

These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to

either V

or V

. If left unconnected, they are internally recognized as V

SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-

OR with other open-drain output devices.

(D) WRITE PROTECT (WP)

The FT24C128A/256A devices have a WP pin to protect the whole EEPROM array from programming.

Programming operations are allowed if WP pin is left un-connected or input to V

. Conversely all programming

functions are disabled if WP pin is connected to V

or V

. Read operations is not affected by the WP pin’s input

level.

MEMORY ORGANIZATION

The FT24C128A/256A devices have 256/512 pages respectively. Since each page has 64 bytes, random word

addressing to FT24C128A/256A will require 14/15 bits data word addresses respectively.

DEVICE OPERATION

(A) SERIAL CLOCK AND DATA TRANSITIONS

The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock

SCL is at V

. Any SDA signal transition may interpret as either a START or STOP condition as described below.

(B) START CONDITION

With SCL

≥V

, a SDA transition from high to low is interpreted as a START condition. All valid commands

must begin with a START condition.

With SCL

≥V

, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write

commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command.

A STOP condition after page or byte write command will trigger the chip into the STANDBY mode after the self-

timed internal programming finish (see Figure 1).

(D) ACKNOWLEDGE

The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM

acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal

occurs on the 9

serial clock after each word.

DS3007J-page3

24C128A,24C256A

WRITE OPERATIONS

(A) BYTE WRITE

A write operation requires two 8-bit data word address following the device address word and ACKNOWLEDGE

signal. Upon receipt of this address, the EEPROM will respond with a “0” and then clock in the first 8-bit data

word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such

as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters

into an internally-timed write cycle state. All inputs are disabled during this write cycle and the EEPROM will not

respond until the writing is completed (figure 3).

(B) PAGE WRITE

The128K/256K EEPROM are capable of 64-byte page write.

A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition

after the first data word is clocked in. The microcontroller can transmit up to 63 more data words after the

EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word

is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 4).

The lower six bits of the data word address are internally incremented following the receipt of each data word. The

higher data word address bits are not incremented, retaining the memory page row location. If more than 64 data

words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be

overwritten.

ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming.

By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9

clock cycle if the

device is still in the self-timed programming mode. However, if the programming completes and the chip has

returned to the STANDBY mode, the device will return a valid ACKNOWLEDGE signal at the 9

clock cycle.

READ OPERATIONS

The read command is similar to the write command except the 8

read/write bit in address word is set to “1”. The three

read operation modes are described as follows:

(A) CURRENT ADDRESS READ

The EEPROM internal address word counter maintains the last read or write address plus one if the power supply

to the device has not been cut off. To initiate a current address read operation, the micro-controller issues a

START bit and a valid device address word with the read/write bit (8

) set to “1”. The EEPROM will response

with an ACKNOWLEDGE signal on the 9

serial clock cycle. An 8-bit data word will then be serially clocked out.

The internal address word counter will then automatically increase by one. For current address read the micro-

controller will not issue an ACKNOWLEDGE signal on the 18

clock cycle. The micro-controller issues a valid

STOP bit after the 18

clock cycle to terminate the read operation. The device then returns to STANDBY mode

(see Figure 5).

(B) SEQUENTIAL READ

The sequential read is very similar to current address read. The micro-controller issues a START bit and a valid

device address word with read/write bit (8

) set to “1”. The EEPROM will response with an ACKNOWLEDGE

signal on the 9

serial clock cycle. An 8-bit data word will then be serially clocked out. Meanwhile the internally

address word counter will then automatically increase by one.

DS3007J-page5

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