74LV123
Dual retriggerable monostable multivibrator with reset
Rev. 7 — 12 December 2011
Product data sheet
1. General description
The 74LV123 is a low-voltage Si-gate CMOS device and is pin and function compatible
with the 74HC123; 74HCT123. It is a dual retriggerable monostable multivibrator which
uses three methods to control the output pulse width:
1. The basic pulse time is programmed by the selection of an external resistor (R
EXT
)
and capacitor (C
EXT
). These are normally connected as shown in
Figure 9.
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired (see
Figure 12).
3. Alternatively, an output delay can be terminated at any time by a LOW-going edge on
input nRD, which also inhibits the triggering (see
Figure 13).
Schmitt-trigger action in the nA and nB inputs makes the circuit highly tolerant of slower
input rise and fall times.
2. Features and benefits
Optimized for low-voltage applications: 1.0 V to 5.5 V
Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
Typical output ground bounce: < 0.8 V at V
CC
= 3.3 V and T
amb
= 25
C
Typical HIGH-level output voltage (V
OH
) undershoot: > 2 V at V
CC
= 3.3 V and
T
amb
= 25
C
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulses
Schmitt-trigger action on all inputs except for the reset input
NXP Semiconductors
74LV123
Dual retriggerable monostable multivibrator with reset
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LV123N
74LV123D
74LV123DB
74LV123PW
74LV123BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
DIP16
SO16
SSOP16
TSSOP16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width
3.9 mm
Version
SOT38-4
SOT109-1
Type number
plastic shrink small outline package; 16 leads; body width SOT338-1
5.3 mm
plastic thin shrink small outline package; 16 leads; body
width 4.4 mm
SOT403-1
DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1
quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
4. Functional diagram
14
15
CX
RCX
&
13
1
14 1CEXT
6 2CEXT
15 1REXT/CEXT
7 2REXT/CEXT
S
Q
1A 1
2A 9
1B 2
2B 10
T
Q
RD
4 1Q
12 2Q
13 1Q
5 2Q
6
7
2
4
3
R
CX
RCX
&
5
9
10
1RD 3
2RD 11
001aae521
12
11
R
001aae522
Fig 1. Logic symbol
Fig 2. IEC logic symbol
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
2 of 24
NXP Semiconductors
74LV123
Dual retriggerable monostable multivibrator with reset
14
15
S
1A
1
T
2
Q
4
Q
1CEXT
1REXT/CEXT
13
1Q
1Q
1B
RD
3
6
7
S
2CEXT
1RD
2REXT/CEXT
2A
9
T
10
Q
5
2Q
Q
12
2Q
2B
RD
11
001aaa610
2RD
Fig 3. Functional diagram
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
3 of 24
NXP Semiconductors
74LV123
Dual retriggerable monostable multivibrator with reset
nREXT/CEXT
V
CC
Q
RD
Q
V
CC
CL
R
CL
V
CC
R
R
CL
A
CL
CL
B
R
001aae524
Fig 4. Logic diagram
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
4 of 24
NXP Semiconductors
74LV123
Dual retriggerable monostable multivibrator with reset
5. Pinning information
5.1 Pinning
74LV123
terminal 1
index area
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
V
CC(1)
8
9
2A
11 2RD
10 2B
GND
1A
2
3
4
5
6
7
1
1B
16 V
CC
15 1REXT/CEXT
14 1CEXT
13 1Q
12 2Q
11 2RD
10 2B
9
001aag678
74LV123
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
1
2
3
4
5
6
7
8
1RD
1Q
2Q
2CEXT
2REXT/CEXT
2A
001aag650
Transparent top view
(1) The die substrate is attached to this
pad using conductive die attach
material. It cannot be used as a supply
pin or input.
Fig 5. Pin configuration for DIP16, SO16,
SSOP16 and TSSOP16
Fig 6. Pin configuration for DHVQFN16
5.2 Pin description
Table 2.
Symbol
1A
1B
1RD
1Q
2Q
2CEXT
2REXT/CEXT
GND
2A
2B
2RD
2Q
1Q
1CEXT
1REXT/CEXT
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
negative-edge triggered input 1
positive-edge triggered input 1
direct reset LOW and positive-edge triggered input 1
active LOW output 1
active HIGH output 2
external capacitor connection 2
external resistor and capacitor connection 2
ground (0 V)
negative-edge triggered input 2
positive-edge triggered input 2
direct reset LOW and positive-edge triggered input 2
active LOW output 2
active HIGH output 1
external capacitor connection 1
external resistor and capacitor connection 1
supply voltage
74LV123
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 12 December 2011
5 of 24
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