CY7C09269V CY7C09279V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
1CY7C025/0251
CY7C09269V/79V/89V
CY7C09369V/79V/89V
3.3V 16K/32K/64K x 16/18
Synchronous Dual-Port Static RAM
Features
•
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
•
6 Flow-Through/Pipelined devices
— 16K x 16/18 organization (CY7C09269V/369V)
— 32K x 16/18 organization (CY7C09279V/379V)
— 64K x 16/18 organization (CY7C09289V/389V)
•
3 Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz operation
• 0.35-micron CMOS for optimum speed/power
•
High-speed clock to data access 6.5
[1, 2]
/7.5
[2]
/9/12 ns
(max.)
•
3.3V low operating power
— Active = 115 mA (typical)
— Standby = 10
µA
(typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
•
Dual Chip Enables for easy depth expansion
• Upper and Lower Byte Controls for Bus Matching
• Automatic power-down
•
Commercial and Industrial temperature ranges
•
Pb-Free 100-pin TQFP Package Available
Logic Block Diagram
R/W
L
UB
L
R/W
R
UB
R
CE
0L
CE
1L
LB
L
OE
L
1
0/1
1
0/1
0
0
CE
0R
CE
1R
LB
R
OE
R
FT/Pipe
L
[3]
I/O
8/9L
–I/O
15/17L
[4]
8/9
0/1
1b 0b 1a 0a
b
a
0a 1a 0b 1b
a
b
0/1
FT/Pipe
R
8/9
I/O
0L
–I/O
7/8L
[5]
A
0L
–A
13/14/15L
8/9
14/15/16
I/O
Control
I/O
Control
I/O
8/9R
–I/O
15/17R
8/9
14/15/16
[3]
I/O
0R
–I/O
7/8R
[5]
A
0R
–A
13/14/15R
[4]
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
CLK
R
ADS
R
CNTEN
R
CNTRST
R
Notes:
1. Call for availability.
2. See page 6 for Load Conditions.
3. I/O
8
–I/O
15
for x16 devices; I/O
9
–I/O
17
for x18 devices.
4. I/O
0
–I/O
7
for x16 devices. I/O
0
–I/O
8
for x18 devices.
5. A
0
–A
13
for 16K; A
0
–A
14
for 32K; A
0
–A
15
for 64K devices.
Cypress Semiconductor Corporation
Document #: 38-06056 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
Revised April 6, 2005
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Functional Description
The CY7C09269V/79V/89V and CY7C09369V/79V/89V are
high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x
16/18 dual-port static RAMs. Two ports are provided,
permitting independent, simultaneous access for reads and
writes to any location in memory.
[6]
Registers on control,
address, and data lines allow for minimal set-up and hold
times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid t
CD2
= 6.5 ns
[1, 2]
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t
CD1
= 18 ns after the
address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
LOW to HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE
0
or LOW on CE
1
for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations.
In the pipelined mode, one cycle is required with CE
0
LOW and
CE
1
HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Pin Configurations
100-Pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A9R
A10R
A11R
A12R
A13R
A14R
A15R
NC
NC
LBR
UBR
CE0R
CE1R
CNTRSTR
GND
R/WR
OER
FT/PIPER
GND
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
[7]
A14L
[8]
A15L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
[7]
[8]
CY7C09289V (64K x 16)
CY7C09279V (32K x 16)
CY7C09269V (16K x 16)
[9]
FT/PIPEL
GND
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
[9]
I/O0R
I/01R
GND
GND
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
VCC
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
Notes:
6. When writing simultaneously to the same location, the final value cannot be guaranteed.
7. This pin is NC for CY7C09269V.
8. This pin is NC for CY7C09269V and CY7C09279V.
9. For CY7C09269V and CY7C09279V, pin #18 connected to V
CC
is pin compatible to an IDT 5V x16 pipelined device; connecting pin #18 and #58 to GND is pin
compatible to an IDT 5V x16 flow-through device.
Document #: 38-06056 Rev. *B
I/O0L
NC
Page 2 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Configurations
(continued)
100-Pin TQFP (Top View)
CNTENR
CNTENL
ADSR
CLKR
ADSL
CLKL
GND
GND
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8L
A7L
A6L
A5L
A4L
A3L
A2L
A1L
A0L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A9L
A10L
A11L
A12L
A13L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A8R
A9R
A10R
A11R
A12R
A13R
A14R
A15R
LBR
UBR
CE0R
CE1R
CNTRSTR
R/WR
GND
OER
FT/PIPER
I/O17R
GND
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
[10]
A14L
[11]
A15L
LBL
UBL
CE0L
CE1L
CNTRSTL
R/WL
OEL
VCC
FT/PIPEL
I/O17L
I/O16L
GND
I/O15L
I/O14L
I/O13L
1/012L
I/O11L
I/O10L
[10]
[11]
CY7C09389V (64K x 18)
CY7C09379V (32K x 18)
CY7C09369V (16K x 18)
I/O9L
I/O8L
I/O7L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O0L
I/O0R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
I/O9R
GND
GND
I/01R
Selection Guide
CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V CY7C09269V/79V/89V
CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V CY7C09369V/79V/89V
-6
[1, 2]
-7
[2]
-9
-12
f
MAX2
(MHz) (Pipelined)
Max. Access Time (ns)
(Clock to Data,
Pipelined)
Typical Operating
Current I
CC
(mA)
Typical Standby Current
for I
SB1
(mA) (Both
Ports TTL Level)
Typical Standby Current
for I
SB3
(µA) (Both Ports
CMOS Level)
100
6.5
83
7.5
67
9
50
12
175
25
155
25
135
20
I/10R
VCC
VCC
115
20
10
µA
10
µA
10
µA
10
µA
Notes:
10. This pin is NC for CY7C09369V.
11. This pin is NC for CY7C09369V and CY7C09379V.
Document #: 38-06056 Rev. *B
Page 3 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Pin Definitions
Left Port
A
0L
–A
15L
ADS
L
Right Port
A
0R
–A
15R
ADS
R
Description
Address Inputs (A
0
–A
14
for 32K, A
0
–A
13
for 16K devices).
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to
access the part using an externally supplied address. Asserting this signal LOW also loads the
burst counter with the address present on the address pins.
Chip Enable Input. To select either the left or right port, both CE
0
AND CE
1
must be asserted
to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Clock Signal. This input can be free running or strobed. Maximum clock input rate is f
MAX
.
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its
respective port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
Data Bus Input/Output (I/O
0
–I/O
15
for x16 devices).
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the
lower byte. (I/O
0
–I/O
8
for x18, I/O
0
–I/O
7
for x16) of the memory array. For read operations both
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O
8/9L
–I/O
15/17L
).
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.
For pipelined mode operation, assert this pin HIGH.
Ground Input.
No Connect.
Power Input.
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >1100V
Latch-Up Current...................................................... >200mA
CE
0L
,CE
1L
CLK
L
CNTEN
L
CE
0R
,CE
1R
CLK
R
CNTEN
R
CNTRST
L
I/O
0L
–I/O
17L
LB
L
CNTRST
R
I/O
0R
–I/O
17R
LB
R
UB
L
OE
L
R/W
L
FT/PIPE
L
GND
NC
V
CC
UB
R
OE
R
R/W
R
FT/PIPE
R
Maximum Ratings
[12]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to V
CC
+0.5V
DC Input Voltage......................................–0.5V to V
CC
+0.5V
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±
300 mV
3.3V
±
300 mV
Note:
12. The voltage on any input or I/O pin can not exceed the power pin during power-up.
Document #: 38-06056 Rev. *B
Page 4 of 19
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Electrical Characteristics
Over the Operating Range
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-6
[1, 2]
Max.
Min.
Min.
Typ.
Parameter
V
OH
V
OL
V
IH
V
IL
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
Description
Output HIGH Voltage (V
CC
= Min.
l
OH
= –4.0 mA)
Output LOW Voltage (V
CC
= Min.
l
OH
= +4.0 mA)
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Operating Current
(V
CC
= Max, I
OUT
= 0 mA)
Outputs Disabled
Com’l.
Indust.
25
95
–10
2.0
0.8
10
175 320
–10
-7
[2]
Max.
Min.
Typ.
-9
Max.
Min.
Typ.
-12
Max.
0.4
2.0
0.8
–10
135
185
20
35
95
105
10
10
85
95
10
230
300
75
85
155
165
250
250
115
125
75
10
250
85
20
70
–10
115
0.8
10
Unit
pF
pF
Typ.
Unit
V
V
V
V
µA
mA
mA
mA
140 mA
mA
µA
µA
100 mA
mA
2.4
0.4
2.4
0.4
2.0
0.8
10
155 275
275 390
25
85
115 175
85
120
2.4
0.4
2.0
2.4
180 mA
Standby Current (Both
Com’l.
[13]
Ports TTL Level)
CE
L
& Indust.
CE
R
≥
V
IH
, f = f
MAX
Standby Current (One Port Com’l.
TTL Level)
[13]
CE
L
| CE
R
≥
Indust.
V
IH
, f = f
MAX
Standby Current (Both
Com’l.
[13]
CE
Ports CMOS Level)
L
Indust.
& CE
R
≥
V
CC
– 0.2V, f = 0
Standby Current (One Port Com’l.
CMOS Level)
[13]
CE
L
| CE
R
Indust.
≥
V
IH
, f = f
MAX
105 165
165 210
10
250
10
10
250
250
125
105 135
95
125 170
Capacitance
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Max.
10
10
Note:
13. CE
L
and CE
R
are internal signals. To select either the left or right port, both CE
0
and CE
1
must be asserted to their active states (CE
0
≤
V
IL
and CE
1
≥
V
IH
).
Document #: 38-06056 Rev. *B
Page 5 of 19
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