CY7C1168KV18-450BZC datasheet, PDF

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CY7C1168KV18-450BZC: Description18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency); File Size586KB，29 Pages; ManufacturerCypress Semiconductor

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CY7C1168KV18-450BZC Overview

18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1166KV18, CY7C1177KV18

CY7C1168KV18, CY7C1170KV18

18-Mbit DDR II+ SRAM Two-Word Burst

Architecture (2.5 Cycle Read Latency)

Features

■

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1166KV18 – 2 M x 8

CY7C1177KV18 – 2 M x 9

CY7C1168KV18 – 1 M x 18

CY7C1170KV18 – 512 K x 36

18 Mbit density (2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36)

550-MHz clock for high bandwidth

Two-word burst for reducing address bus frequency

Double data rate (DDR) interfaces

(data transferred at 1100 MHz) at 550 MHz

Available in 2.5 clock cycle latency

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

Data valid pin (QVLD) to indicate valid data on the output

Synchronous internally self-timed writes

DDR II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

Operates similar to DDR I device with one cycle read latency

when DOFF is asserted LOW

Core V

= 1.8 V ± 0.1 V; I/O V

DDQ

= 1.4 V to V

DD[1]

❐

Supports both 1.5 V and 1.8 V I/O supply

HSTL inputs and variable drive HSTL output buffers

Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

Offered in both Pb-free and non Pb-free packages

JTAG 1149.1 compatible test access port

Phase-locked loop (PLL) for accurate data placement

Functional Description

The CY7C1166KV18, CY7C1177KV18, CY7C1168KV18, and

CY7C1170KV18 are 1.8 V synchronous pipelined SRAMs

equipped with DDR II+ architecture. The DDR II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1166KV18), 9-bit words (CY7C1177KV18), 18-bit

words (CY7C1168KV18), or 36-bit words (CY7C1170KV18) that

burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■

Table 1. Selection Guide

Description

Maximum operating frequency

Maximum operating current

x18

x36

550 MHz

550

630

650

820

500 MHz

500

590

600

760

450 MHz

450

550

560

700

400 MHz

400

500

510

640

Unit

MHz

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

DDQ

= 1.4 V to V

Cypress Semiconductor Corporation

Document Number: 001-58913 Rev. *C

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised February 24, 2011

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