CY7C1393JV18
CY7C1394JV18
18 Mbit DDR II SIO SRAM Two Word
Burst Architecture
Features
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Functional Description
The CY7C1393JV18, and CY7C1394JV18 are 1.8V
Synchronous Pipelined SRAMs, equipped with Double Data
Rate Separate IO (DDR II SIO) architecture. The DDR II SIO
consists of two separate ports: the read port and the write port to
access the memory array. The read port has data outputs to
support read operations and the write port has data inputs to
support write operations. The DDR II SIO has separate data
inputs and data outputs to completely eliminate the need to
‘turnaround’ the data bus required with common IO devices.
Access to each port is accomplished through a common address
bus. Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C or C
is not provided. Each address location is associated with two
18-bit words in the case of CY7C1393JV18, and two 36-bit
words in the case of CY7C1394JV18 that burst sequentially into
or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K/K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self timed write circuitry.
18 Mbit Density (1M x 18, 512K x 36)
300 MHz Clock for High Bandwidth
Two word Burst for reducing Address Bus Frequency
Double Data Rate (DDR) Interfaces
(data transferred at 600 MHz) at 300 MHz
Two Input Clocks (K and K) for Precise DDR Timing
❐
SRAM uses rising edges only
Two Input Clocks for Output Data (C and C) to Minimize Clock
Skew and Flight Time mismatches
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
Synchronous Internally self timed Writes
DDR II operates with 1.5 cycle Read Latency when the DLL is
enabled
Operates similar to a DDR I Device with one Cycle Read
Latency in DLL Off Mode
1.8V Core Power Supply with HSTL Inputs and Outputs
Variable Drive HSTL Output Buffers
Expanded HSTL Output Voltage (1.4V–V
DD
)
Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible Test Access Port
Delay Lock Loop (DLL) for Accurate Data Placement
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Configurations
CY7C1393JV18 – 1M x 18
CY7C1394JV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x18
x36
300 MHz
300
865
935
250 MHz
250
725
770
Unit
MHz
mA
Cypress Semiconductor Corporation
Document #: 001-44698 Rev. *C
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 25, 2009
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CY7C1393JV18
CY7C1394JV18
Logic Block Diagram (CY7C1393JV18)
D
[17:0]
18
Write Add. Decode
Read Add. Decode
A
(18:0)
19
Address
Register
Write
Data Reg
Write
Data Reg
512K x 18 Array
512K x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
CLK
Gen.
Read Data Reg.
36
18
Control
Logic
18
Reg.
Reg.
Reg. 18
18
R/W
V
REF
LD
BWS
[1:0]
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1394JV18)
D
[35:0]
36
Write Add. Decode
Read Add. Decode
A
(17:0)
18
Address
Register
Write
Data Reg
Write
Data Reg
256K x 18 Array
256K x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
CLK
Gen.
Read Data Reg.
72
36
Control
Logic
36
Reg.
Reg.
Reg. 36
36
R/W
V
REF
LD
BWS
[3:0]
CQ
36
Q
[35:0]
Document #: 001-44698 Rev. *C
Page 2 of 23
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CY7C1393JV18
CY7C1394JV18
Pin Configuration
The pin configurations for CY7C1393JV18, and CY7C1394JV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1393JV18 (1M x 18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
1
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/288M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/72M
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/144M NC/36M
CY7C1394JV18 (512K x 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
Q29
Q30
D30
DOFF
D31
Q32
Q33
D33
D34
Q35
TDO
2
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
D18
D19
Q19
Q20
D21
Q22
V
DDQ
D23
Q23
D24
D25
Q25
Q26
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
BWS
2
BWS
3
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
BWS
1
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
D17
D16
Q16
Q15
D14
Q13
V
DDQ
D12
Q12
D11
D10
Q10
Q9
A
10
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
NC/288M NC/72M
NC/36M NC/144M
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document #: 001-44698 Rev. *C
Page 3 of 23
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CY7C1393JV18
CY7C1394JV18
Pin Definitions
Pin Name
D
[x:0]
IO
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Pin Description
Data Input Signals.
Sampled on the rising edge of K and K clocks during valid write operations.
CY7C1393JV18 - D
[17:0]
CY7C1394JV18 - D
[35:0]
Synchronous Load.
This input is brought LOW when a bus cycle sequence is defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period
of bus activity).
Byte Write Select 0, 1, 2 and 3
−
Active LOW.
Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1393JV18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
.
CY7C1394JV18
−
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,BWS
2
controls D
[26:18]
and BWS
3
controls
D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and is not written into the device.
Address Inputs.
Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
1M x 18 (2 arrays each of 512K x 18) for CY7C1393JV18, and 512K x 36 (2 arrays each of 256K x 36)
for CY7C1394JV18. Therefore, only 19 address inputs are needed to access the entire memory array of
CY7C1393JV18 and 18 address inputs for CY7C1394JV18. These inputs are ignored when the appro-
priate port is deselected.
Data Output Signals.
These pins drive out the requested data during a read operation. Valid data is
driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q
[x:0]
are automatically tri-stated.
CY7C1393JV18
−
Q
[17:0]
CY7C1394JV18
−
Q
[35:0]
Synchronous Read/Write Input.
When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
Positive Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See
Application Example
on page 7 for further details.
Negative Input Clock for Output Data.
C is used in conjunction with C to clock out the read data from
the device. C and C are used together to deskew the flight times of various devices on the board back to
the controller. See
Application Example
on page 7 for further details.
Positive Input Clock Input.
The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on the rising
edge of K.
Negative Input Clock Input.
K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
when in single clock mode.
CQ Referenced with Respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the table
Switching Characteristics
on page 20.
CQ Referenced with Respect to C.
This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the table
Switching Characteristics
on page 20.
Output Impedance Matching Input.
This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin is connected directly to V
DDQ
, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
LD
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
A
Input-
Synchronous
Q
[x:0]
Outputs-
Synchronous
R/W
Input-
Synchronous
Input Clock
C
C
Input Clock
K
Input Clock
K
CQ
Input Clock
Echo Clock
CQ
Echo Clock
ZQ
Input
Document #: 001-44698 Rev. *C
Page 4 of 23
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CY7C1393JV18
CY7C1394JV18
Pin Definitions
Pin Name
DOFF
Input
IO
(continued)
Pin Description
DLL Turn Off
−
Active Low.
Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR I mode
when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
TDO for JTAG.
TCK Pin for JTAG.
TDI Pin for JTAG.
TMS Pin for JTAG.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Not Connected to the Die.
Can be tied to any voltage level.
Reference Voltage Input.
Static input used to set the reference level for HSTL inputs, Outputs, and AC
measurement points.
TDO
TCK
TDI
TMS
NC
NC/36M
NC/72M
Output
Input
Input
Input
N/A
N/A
N/A
NC/144M N/A
NC/288M N/A
V
REF
V
DD
V
SS
V
DDQ
Input-
Reference
Power Supply
Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply
Power Supply Inputs for the Outputs of the Device.
Document #: 001-44698 Rev. *C
Page 5 of 23
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