Programable Spread spectrum precentage for EMI control
Uses external 14.318MHz crystal
Select pins for frequency select
Pin Configuration
REF0
VDD
X1
X2
GND
SDATA
SCLK
GNDA
VDDA
SEL1A
PCI1A_0
PCI1A_1
VDD33
GND
PCI1A_2
PCI1A_3
GND
VDD33
PCI1A_4
PCI1A_5
VDD33
GND
PCI1A_6
PCI1A_7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48MHz
GND
VDD48
SPREAD
VDDA
GNDA
SEL2B
PCI2B_2
PCI2B_1
GND
VDD66
PCI2B_0
SEL2A
PCI2A_2
PCI2A_1
VDD2A
GND
PCI2A_0
SEL1B
PCI1B_2
PCI1B_1
GND
VDD1B
PCI1B_0
Features:
Key Specifications:
• PCI – PCI output skew within same bank @ 33MHz: <170ps
•
•
•
•
•
•
PCI – PCI output skew within same bank@ 66MHz: <340ps
Cycle to Cycle Jitter PCI @ 33MHz: <200ps
Cycle to Cycle Jitter PCI @ 66MHz: <200ps
Cycle to Cycle Jitter 48MHz: <350ps
Cycle to Cycle Jitter REF: <500ps
Slew Rate: 1.5 - 4 V/ns. (PCI spec.)
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
48MHz
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
PCI
DIVDER
REF0
8
PCI1A (7:0)
PCI
DIVDER
3
PCI2A (2:0)
SDATA
SCLK
SELA (2:1)
SELB (2:1)
SPREAD
Control
Logic
Config.
Reg.
PCI
DIVDER
3
PCI1B (2:0)
PCI
DIVDER
3
PCI2B (2:0)
Power Groups:
VDDA = Analog Power
GNDA = Analog Ground
0663B—09/04/03
PRODUCT PREVIEW
documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
ICS951601
ICS951601
Preliminary Product Preview
Pin Descriptions
Pin number
1
2, 13, 18, 21, 26,
33, 38, 46
3
4
9, 44
10, 30, 36, 42
5, 14, 17, 22, 27,
32, 39, 47
6
7
8, 43
24, 23, 20, 19,
16, 15, 12, 11,
29, 28, 25
35, 34, 31
41, 40, 37
45
48
Pin name
REF0
VDD
X1
X2
VDDA
SELxx
GND
SDATA
SCLK
GNDA
PCI1A (7:0)
PCI1B (2:0)
PCI2A (2:0)
PCI2B (2:0)
SPREAD
48MHz
Type
OUT
PWR
IN
OUT
PWR
IN
PWR
I/O
IN
PWR
OUT
OUT
OUT
OUT
IN
OUT
Description
Reference output
3.3V Power supply
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Analog 3.3V Power supply
Real time PCI output frequency selection pins
Ground pins
Data pin for I
2
C circuitry 5V tolerant
Clock input of I
2
C input
Analog ground pins
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
PCI clock outputs, selectable to be either
33.33 or 66.66MHz at 3.3V.
Enables Spread Spectrum, default is on.
Fixed 48MHz clock output for USB.
0663B—09/04/03
2
ICS951601
Preliminary Prouct Preview
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends a dummy command code
• ICS clock will
acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will
acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will
acknowledge
each byte
one at a
time
.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the
byte count
• Controller (host) acknowledges
• ICS clock sends first byte
(Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Dummy Byte Count
ACK
Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
0663B—09/04/03
3
ICS951601
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit2 Bit7 Bit6 Bit5 Bit4 66MHZ 33MHz
FEATURES
FS4 FS3 FS2 FS1 FS0
66
33
-0.25 % down spread
0
0
0
0
0
66
33
-0.5 % down spread
0
0
0
0
1
66
33
-1.0 % down spread
0
0
0
1
0
66
33
-1.5 % down spread
0
0
0
1
1
66
33
+ 0.25 % center spread
0
0
1
0
0
66
33
+0.5 % center spread
0
0
1
0
1
66
33
+ 1.0 % center spread
0
0
1
1
0
66.6
33.3
+1.5 % center spread
0
0
1
1
1
67.32
33.66
2% over-clocking
0
1
0
0
0
68.64
34.32
4% over-clocking
0
1
0
0
1
69.96
34.98
6% over-clocking
0
1
0
1
0
Bit
72.6
36.3
10% over-clocking
0
1
0
1
1
2,7:4 0
65.27
32.63
2% under- clocking
1
1
0
0
63.96
31.97
2% under- clocking
0
1
1
0
1
62.6
31.3
2% under- clocking
0
1
1
1
0
60
30
2% under- clocking
0
1
1
1
1
66.6
33.3
-1.4 % down spread
1
0
0
0
0
66.6
33.3
-1.6 % down spread
1
0
0
0
1
66.6
33.3
-1.8 % down spread
1
0
0
1
0
66.6
33.3
-2.0 % down spread
1
0
0
1
1
66.6
33.3
+ 1.4 % center spread
1
0
1
0
0
66.6
33.3
+ 1.6 % center spread
1
0
1
0
1
66.6
33.3
+ 1.8 % center spread
1
0
1
1
0
66.6
33.3
+ 2.0 % center spread
1
0
1
1
1
0-Frequency and Spread is seleced by hardware select. Latched input
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