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PI74ALVCHR162245

Description
3.3V 16-Bit Bidirectional Transceiver with 3-State Output
File Size198KB,4 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet View All

PI74ALVCHR162245 Overview

3.3V 16-Bit Bidirectional Transceiver with 3-State Output

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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74ALVCHR162245
3.3V 16-Bit Bidirectional Transceiver
with 3-State Output
Product Features
• PI74ALVCHR162245 is designed for low voltage operation
• Vcc = 2.3V to 3.6V
• Hysteresis on all inputs
• Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
• Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
• All output ports have equivilent 26Ω series resistors:
No external resistors are required
• Bus Hold retains last active bus state during 3-state
eliminating the need for external pull-up resistors
• Industrial operation at -40°C to +85°C
• Packages available:
– 48-pin 240-mil wide plastic TSSOP (A)
– 48-pin 300-mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology to achieve industry-leading speed grades.
The PI74ALVCHR162245 is a 16-bit bidirectional transceiver
designed for asynchronous two-way communication between data
buses. The direction control input pin (xDIR) determines the
direction of data flow through the bidirectional transceiver. The
Direction and Output Enable controls are designed to operate this
device as either two independent 8-bit transceivers or one 16-bit
transceiver. The output enable (OE) input, when HIGH, disables
both A and B ports by placing them in HIGH Z condition.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pull-up resistor; the
minimum value of the resistor is determined by the current sinking
ability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1
DIR
2
DIR
1
OE
2
OE
1
A
0
1
B
0
1
A
1
1
B
1
1
A
2
1
B
2
1
A
3
1
B
3
1
A
4
1
B
4
1
A
5
1
B
5
1
A
6
1
B
6
1
A
7
1
B
7
2
A
0
2
B
0
2
A
1
2
B
1
2
A
2
2
B
2
2
A
3
2
B
3
2
A
4
2
B
4
2
A
5
2
B
5
2
A
6
2
B
6
2
A
7
2
B
7
1
PS8343
10/09/98

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