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MT9VDDF6472PHG-265A1

Description
Memory IC, 64MX72, CMOS, PDMA200
Categorystorage    storage   
File Size378KB,26 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric View All

MT9VDDF6472PHG-265A1 Overview

Memory IC, 64MX72, CMOS, PDMA200

MT9VDDF6472PHG-265A1 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Objectid108997125
package instructionDIMM, DIMM200,24
Reach Compliance Codeunknown
ECCN codeEAR99
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeR-PDMA-N200
memory density4831838208 bit
memory width72
Number of terminals200
word count67108864 words
character code64000000
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX72
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIMM
Encapsulate equivalent codeDIMM200,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
power supply2.5 V
Certification statusNot Qualified
refresh cycle8192
Maximum standby current0.04 A
Maximum slew rate2.8 mA
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
256MB, 512MB: (x72, ECC, PLL, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM Small-Outline DIMM
MT9VDDF3272PH(I) – 256MB,
MT9VDDF6472PH(I) – 512MB
For component specifications, refer to Micron’s Web site:
www.micron.com/products/ddrsdram
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Supports ECC error detection and correction
• Fast data transfer rates: PC2100 and PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 256MB (32 Meg x 72) and 512MB (64 Meg x 72)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/re-
ceived with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Programmable READ CAS latency
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Bidirectional data strobe (DQS) transmitted/re-
ceived with data—i.e., source-synchronous data
capture
• Gold edge contacts
Figure 1:
200-Pin SODIMM (MO-224)
Height 1.25in (31.75mm)
Options
• Operating Temperature Range
Commercial (0°C
T
A
+70°C)
Industrial (-40°C
T
A
+85°C)
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
• Clock frequency, speed, CAS latency
2
6ns (267 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2
7.5ns (133 MHz), 266 MT/s, CL = 2.5
• PCB Height
1.25in. (31.75mm)
Marking
None
I
1
G
Y
1
-335
-262
1
-26A
1
-265
Notes: 1. Consult Micron for product availability.
2. CL = Device CAS (READ) latency.
PDF: 09005aef81eef7d4/Source: 09005aef81eef0df
DDF9C32_64x72PH_1.fm - Rev. A 1/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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