The KSZ8873MLL/FLL/RLL are highly-integrated 3-port
switches on a chip ICs in the industry’s smallest footprint.
They are designed to enable a new generation of low port
count, cost-sensitive, and power-efficient 10/100Mbps
switch systems. Low power consumption, advanced power
management and sophisticated QoS features (e.g., IPv6
priority classification support) make these devices ideal for
IPTV, IP-STB, VoIP, automotive, and industrial
applications.
The KSZ8873 family is designed to support the GREEN
requirement in today’s switch systems. Advanced power
management schemes include hardware power down,
software power down, per port power down and the energy
detect mode that shuts downs the transceiver when a port
is idle.
KSZ8873MLL/FLL/RLL also offers a by-pass mode. In this
mode, the processor connected to the switch through the
MII interface can be shut down without impacting the
normal switch operation.
The configurations provided by the KSZ8873 family
enables the flexibility to meet requirements of different
applications:
•
•
•
KSZ8873MLL: Two 10/100BASE-T/TX transceivers
and one MII interface.
KSZ8873RLL: Two 10/100BASE-T/TX transceivers
and one RMII interface.
KSZ8873FLL: Two 100BASE-FX transceivers and one
MII interface.
The device is available in RoHS-compliant 64-pin LQFP
package. Industrial-grade and qualified AEC-Q100
Automotive-grade version are also available (see
Ordering
Information
section)
Datasheets and support documentation are available on
Micrel’s web site at:
www.micrel.com.
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 •
http://www.micrel.com
September 20, 2013
Revision 1.6
Micrel, Inc.
KSZ8873MLL/FLL/RLL
Features
Advanced Switch Features
•
IEEE 802.1q VLAN support for up to 16 groups (full-range
of VLAN IDs)
•
VLAN ID tag/untag options, per port basis
•
IEEE 802.1p/q tag insertion or removal on a per port basis
(egress)
•
Programmable rate limiting at the ingress and egress on a
per port basis
•
Broadcast storm protection with % control (global and per
port basis)
•
IEEE 802.1d rapid spanning tree protocol support
•
tail tag mode (1 byte added before FCS) support at port3 to
inform the processor which ingress port receives the
packet and its priority
•
Bypass feature which Automatically sustains the switch
function between Port1 and Port2 when CPU (Port 3
interface) goes to the sleep mode
•
Self-address filtering
•
Individual MAC address for port1 and port2
•
Support RMII interface and 50 MHz reference clock output
•
MAC MII interface supports both MAC mode and PHY
mode
•
IGMP snooping (Ipv4) support for multicast packet Filtering
•
IPv4/IPv6 QoS support.
•
MAC filtering function to forward unknown unicast packets
to specified port
Comprehensive Configuration Register Access
•
Serial management interface (SMI) to all internal
registers
•
MII management (MIIM) interface to PHY registers
•
High speed SPI and I
2
C Interface to all internal registers
•
I/0 pins strapping and EEPROM to program selective
registers in unmanaged switch mode
•
Control registers configurable on the fly (port-priority,
802.1p/d/q, AN…)
QoS/CoS Packet Prioritization Support
•
Per port, 802.1p and DiffServ-based
•
Re-mapping of 802.1p priority field per port basis Four
priority levels
Proven Integrated 3-Port 10/100 Ethernet Switch
•
3rd generation switch with three MACs and two
•
PHYs fully compliant with IEEE 802.3u standard
•
Non-blocking switch fabric assures fast packet delivery by
utilizing an 1K MAC address lookup table and a store-and-
forward architecture
•
Full duplex IEEE 802.3x flow control (PAUSE) with force
mode option
•
Half-duplex back pressure flow control
•
HP Auto MDI-X for reliable detection of and correction for
straight-through and crossover cables with disable and
enable option
•
Micrel LinkMD
®
TDR-based cable diagnostics permit
identification of faulty copper cabling on Port 2
•
Comprehensive LED Indicator support for link, activity,
full/half duplex and 10/100 speed
•
HBM ESD Rating 3kV
Switch Monitoring Features
•
Port mirroring/monitoring/sniffing: ingress and/or egress
traffic to any port or MII
•
MIB counters for fully compliant statistics gathering 34 MIB
counters per port
•
Loopback modes for remote diagnostic of failure
Low Power Dissipation:
•
Full-chip hardware power-down (register configuration not
saved)
•
Full-chip software power-down (register configuration not
saved)
•
Energy-detect mode support
•
Dynamic clock tree shutdown feature
•
Per port based software power-save on PHY (idle link
detection, register configuration preserved)
•
Voltages: Single 3.3V supply with internal 1.8V LDO for
3.3V VDDIO
•
Optional 3.3V, 2.5V and 1.8V for VDDIO
•
Transceiver power 3.3V for VDDA_3.3
Industrial Temperature Range: –40°C to +85°C
Available in 64-Pin LQFP, Lead-Free package
Applications
•
•
•
•
•
•
•
•
•
VoIP phone
Set-top/game box
Automotive Ethernet
Industrial control
IPTV POF
SOHO residential gateway
Broadband gateway/firewall/VPN
Integrated DSL/cable modem
Wireless LAN access point + gateway
•
Standalone 10/100 switch
September 20, 2013
2
Revision 1.6
Micrel, Inc.
KSZ8873MLL/FLL/RLL
Ordering Information
Part Number
KSZ8873MLL
KSZ8873MLLI
KSZ8873MLL AM
KSZ8873FLL
KSZ8873FLLI
KSZ8873RLL
KSZ8873RLLI
KSZ8873RLLU
Temperature Range
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
Package
64-Pin LQFP
64-Pin LQFP
64-Pin LQFP
64-Pin LQFP
64-Pin LQFP
64-Pin LQFP
64-Pin LQFP
64-Pin LQFP
Lead Finish/Grade
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Automotive grade 3
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Commercial
Pb-Free/Industrial
Pb-Free/Automotive grade 3
Revision History
Revision
1.0
1.1
Date
03/25/08
06/26/09
09/08/09
1.2
Summary of Changes
Initial release
Combined Register Description to initial release.
Removed LinkMD feature.
Updated the Electrical Characteristics.
Added LinkMD feature on Port 2.
Fixed the typo on Register 194
Modified Pin 31(SMRXD31) description.
Removed Turbo MII feature and its timing, add MDC/MDIO timing, update the descriptions of the by-pass
mode, tag insertion, power management, pins, registers, and so on. Update max rating, RMII timing and
electrical characteristics.
Updated Register 6 with strap pins description, Junction Thermal and so on. Added the descriptions of the
registers from Registers 175-186. Added a note for port register control 12, updated the description for some
registers, updated reset timing diagram.
Updated description for MDC/MDIO SMI mode and IGMP mode. ESD rating updated to 3kV. Update data of
lead temperature.
Correct typo error in ordering information table.
Correct typo error for MDI-X status in the PHY Register 31.
Add or update the notes for Pin SCRS3 description, the port register control 0 bit 2 and the port register
control 5 bit 7. Update the operation voltage Min/Max for different VDDIO. Update the pin description for Pin
30 and Pin 33. Change TTL I/O to CMOS I/O. Update the Register 166 description and the default value. Add
KSZ8873RLLU Automotive device in order information Table. Add a note for Register 195 bits [5:4].
09/23/09
10/01/09
1.3
08/10/10
1.4
05/25/11
1.5
07/28/11
11/01/11
11/15/11
1.6
04/11/13
September 20, 2013
3
Revision 1.6
Micrel, Inc.
KSZ8873MLL/FLL/RLL
Contents
General Description ................................................................................................................................................................ 1
Features .................................................................................................................................................................................. 2
Ordering Information ............................................................................................................................................................... 3
Revision History ...................................................................................................................................................................... 3
List of Figures ........................................................................................................................................................................ 10
List of Tables ......................................................................................................................................................................... 11
100BASE-FX Signal Detection .......................................................................................................................................... 20
MDI/MDI-X Auto Crossover ............................................................................................................................................... 20
Functional Overview: Power Management ........................................................................................................................... 25
Normal Operation Mode .................................................................................................................................................... 25
Hardware Power Down ...................................................................................................................................................... 26
Functional Overview: MAC and Switch ................................................................................................................................. 27
MAC Operation .................................................................................................................................................................. 30
Inter Packet Gap (IPG) .................................................................................................................................................. 30
Late Collision ................................................................................................................................................................. 30
Full Duplex Flow Control ................................................................................................................................................ 30
Port Individual MAC Address and Source Port Filtering ................................................................................................ 31
MII Interface Operation ...................................................................................................................................................... 31
QoS Priority Support .......................................................................................................................................................... 37
Spanning Tree Support ..................................................................................................................................................... 38
Rapid Spanning Tree Support ........................................................................................................................................... 39
IGMP Support .................................................................................................................................................................... 40
IGMP Send-Back to the Subscribed Port ...................................................................................................................... 40
Port Mirroring Support ....................................................................................................................................................... 40
Rate Limiting Support ........................................................................................................................................................ 41
Unicast MAC Address Filtering.......................................................................................................................................... 41
I C Master Serial Bus Configuration .............................................................................................................................. 41
2
I C Slave Serial Bus Configuration ................................................................................................................................ 42
SPI Slave Serial Bus Configuration ............................................................................................................................... 43
Loopback Support ............................................................................................................................................................. 46
MII Management (MIIM) Registers........................................................................................................................................ 48
Global Registers ................................................................................................................................................................ 53
Port Registers .................................................................................................................................................................... 53
Advanced Control Registers .............................................................................................................................................. 53
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