74LVC11BQ,115 datasheet, PDF - EEWORLD Datasheet

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74LVC11BQ,115: Descriptionlogic gates 3.3V triple 3-input; Categorylogic logic; File Size117KB，15 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC11BQ,115 Overview

logic gates 3.3V triple 3-input

74LVC11BQ,115 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconduc
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	QFN
package instruction	HVQCCN, LCC14,.1X.12,20
Contacts	14
Manufacturer packaging code	SOT762-1
Reach Compliance Code	compli
Is Samacsys	N
series	LVC/LCX/Z
JESD-30 code	R-PQCC-N14
JESD-609 code	e4
length	3 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	AND GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	3
Number of entries	3
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC14,.1X.12,20
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	7.2 ns
propagation delay (tpd)	7 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	1.2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	2.5 mm
Base Number Matches	1

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74LVC11

Triple 3-input AND gate

Rev. 6 — 17 November 2011

Product data sheet

1. General description

The 74LVC11 provides three 3-input AND functions.

2. Features and benefits



Wide supply voltage range from 1.2 V to 3.6 V

Inputs accept voltages up to 5.5 V

CMOS low power consumption

Direct interface with TTL levels

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range

74LVC11D

74LVC11DB

74LVC11PW

74LVC11BQ

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

Name

SO14

SSOP14

TSSOP14

Description

plastic small outline package; 14 leads;

body width 3.9 mm

plastic shrink small outline package; 14 leads;

body width 5.3 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

Version

SOT108-1

SOT337-1

SOT402-1

SOT762-1

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5



0.85 mm

74LVC11BQ,115 Related Products

	74LVC11BQ,115	74LVC11DB,112	74LVC11PW,112	74LVC11PW,118	74LVC11D,112	74LVC11DB,118	74LVC11D,118
Description	logic gates 3.3V triple 3-input	logic gates 3.3V triple 3-input	logic gates 3.3V triple 3-input	logic gates triple 3-IN and gate	logic gates 3.3V triple 3-input	logic gates 3.3V triple 3-input	logic gates 3.3V triple 3-input
Brand Name	NXP Semiconduc	NXP Semiconduc	NXP Semiconduc	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor	NXP Semiconductor
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	NXP	NXP	NXP	NXP	NXP	NXP	NXP
Parts packaging code	QFN	SSOP1	TSSOP	TSSOP	SOIC	SSOP1	SOIC
package instruction	HVQCCN, LCC14,.1X.12,20	5.30 MM, PLASTIC, MO-150, SOT-337-1, SSOP-14	4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14	4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14	SOP, SOP14,.25	SSOP, SSOP14,.3	SOP, SOP14,.25
Contacts	14	14	14	14	14	14	14
Manufacturer packaging code	SOT762-1	SOT337-1	SOT402-1	SOT402-1	SOT108-1	SOT337-1	SOT108-1
Reach Compliance Code	compli	compli	compli	compliant	compliant	compliant	compliant
series	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PQCC-N14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
length	3 mm	6.2 mm	5 mm	5 mm	8.65 mm	6.2 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF	50 pF
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE
MaximumI(ol)	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	1	1	1	1	1	1
Number of functions	3	3	3	3	3	3	3
Number of entries	3	3	3	3	3	3	3
Number of terminals	14	14	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	SSOP	TSSOP	TSSOP	SOP	SSOP	SOP
Encapsulate equivalent code	LCC14,.1X.12,20	SSOP14,.3	TSSOP14,.25	TSSOP14,.25	SOP14,.25	SSOP14,.3	SOP14,.25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE
method of packing	TAPE AND REEL	TUBE	TUBE	TAPE AND REEL	TUBE	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
propagation delay (tpd)	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns	7 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	NO	NO	NO	NO	NO	NO
Maximum seat height	1 mm	2 mm	1.1 mm	1.1 mm	1.75 mm	2 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V
Nominal supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD	NICKEL/PALLADIUM/GOLD (NI/PD/AU)	NICKEL/PALLADIUM/GOLD (NI/PD/AU)	Nickel/Palladium/Gold (Ni/Pd/Au)	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	NO LEAD	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.65 mm	0.65 mm	0.65 mm	1.27 mm	0.65 mm	1.27 mm
Terminal location	QUAD	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
width	2.5 mm	5.3 mm	4.4 mm	4.4 mm	3.9 mm	5.3 mm	3.9 mm
JESD-609 code	e4	e4	-	-	e4	e4	e4
Prop。Delay @ Nom-Sup	-	-	-	7.2 ns	7.2 ns	7.2 ns	7.2 ns

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