a
FEATURES
Four Complete Voltage Output DACs
Data Register Readback Feature
“Reset to Zero” Override
Multiplying Operation
Double-Buffered Latches
Surface Mount and DIP Packages
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Automatic Test Equipment
Robotics
Process Control
Disk Drives
Instrumentation
Avionics
PRODUCT DESCRIPTION
Monolithic
12-Bit Quad DAC
AD664
PIN CONFIGURATIONS
44-Pin Package
The AD664 is four complete 12-bit, voltage-output DACs on
one monolithic IC chip. Each DAC has a double-buffered input
latch structure and a data readback function. All DAC read and
write operations occur through a single microprocessor-compatible
I/O port.
The I/O port accommodates 4-, 8- or 12-bit parallel words al-
lowing simple interfacing with a wide variety of microprocessors.
A reset to zero control pin is provided to allow a user to simulta-
neously reset all DAC outputs to zero, regardless of the contents
of the input latch. Any one or all of the DACs may be placed in
a transparent mode allowing immediate response by the outputs
to the input data.
The analog portion of the AD664 consists of four DAC cells,
four output amplifiers, a control amplifier and switches. Each
DAC cell is an inverting R-2R type. The output current from
each DAC is switched to the on-board application resistors and
output amplifier. The output range of each DAC cell is pro-
grammed through the digital I/O port and may be set to unipo-
lar or bipolar range, with a gain of one or two times the reference
voltage. All DACs are operated from a single external reference.
The functional completeness of the AD664 results from the
combination of Analog Devices’ BiMOS II process, laser-trimmed
thin-film resistors and double-level metal interconnects.
PRODUCT HIGHLIGHTS
28-Pin DIP Package
4. The asynchronous RESET control returns all D/A outputs
to zero volts.
5. DAC-to-DAC matching performance is specified and tested.
6. Linearity error is specified to be 1/2 LSB at room tempera-
ture and 3/4 LSB maximum for the K, B and T grades.
7. DAC performance is guaranteed to be monotonic over the
full operating temperature range.
8. Readback buffers have tristate outputs.
9. Multiplying-mode operation allows use with fixed or vari-
able, positive or negative external references.
10. The AD664 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD664/883B data sheet for detailed
specifications.
1. The AD664 provides four voltage-output DACs on one chip
offering the highest density 12-bit D/A function available.
2. The output range of each DAC is fully and independently
programmable.
3. Readback capability allows verification of contents of the in-
ternal data registers.
REV.
D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:
781/329-4700
Fax:
781/461-3113
AD664–SPECIFICATIONS
Model
RESOLUTION
ANALOG OUTPUT
Voltage Range
1
UNI Versions
BIP Versions
Output Current
Load Resistance
Load Capacitance
Short-Circuit Current
ACCURACY
Gain Error
Unipolar Offset
Bipolar Zero
3
Linearity Error
4
Linearity T
MIN
to T
MAX
Differential Linearity
Differential Linearity T
MIN
to T
MAX
Gain Error Drift
Unipolar 0 V to +10 V Mode
Bipolar –5 V to +5 V Mode
Bipolar –10 V to +10 V Mode
Unipolar Offset Drift
Unipolar 0 V to +10 V Mode
Bipolar Zero Drift
Bipolar –5 V to +5 V Mode
Bipolar –10 V to +10 V Mode
REFERENCE INPUT
Input Resistance
Voltage Range
6
POWER REOUIREMENTS
V
LL
I
LL
@ V
IH
, V
IL
= 5 V, 0 V
@ V
IH
, V
IL
= 2.4 V, 0.4 V
V
CC
/V
EE
I
CC
I
EE
Total Power
ANALOG GROUND CURRENT
7
MATCHING PERFORMANCE
Gain
8
Offset
9
Bipolar Zero
10
Linearity
11
CROSSTALK
Analog
Digital
DYNAMIC PERFORMANCE (R
L
= 2 kΩ, C
L
= 500 pF)
Settling Time to
±
1/2 LSB
Off←Bits→On, GAIN = 1, V
REF
= 10
Settling Time to
±
1/2 LSB
–10←V
REF
→10
V, GAIN = 1, Bits On
Glitch Impulse
MULTIPLYING MODE PERFORMANCE
Reference Feedthrough @ 1 kHz
Reference –3 dB Bandwidth
POWER SUPPLY GAIN SENSITIVITY
11.4 V←V
CC
→16.5
V
–16.5 V←V
EE
→–11.4
V
4.5 V←V
LL
→5.5
V
(V
LL
= +5 V, V
CC
= +15 V, V
EE
= –15 V, V
REF
= +10 V, T
A
= +25 C
unless otherwise noted)
Min
JN/JP/AD/AJ/SD
Typ
Max
12
12
KN/KP/BD/BJ/BE/TD/TE
Min
Typ
Max
*
*
Units
Bits
0
V
EE
+ 2.0
2
5
2
25
V
CC
– 2.0
2
V
CC
– 2.0
2
*
*
*
*
*
*
500
40
*
*
*
Volts
Volts
mA
kΩ
pF
mA
LSB
LSB
LSB
LSB
LSB
LSB
–7
±
3
7
–2
±
1/2
2
–3
±
3/4
3
–3/4
±
1/2
3/4
–1
±
3/4
1
–3/4
3/4
Monotonic @ All Temperatures
–12
–12
–12
–3
–12
–12
1.3
V
EE
+ 2.0
2
4.5
5.0
0.1
3
11.4
12
15
400
–600
–6
–2
–3
–1.5
±
400
±
3
±
1/2
±
1
±
1/2
±
7
±
7
±
7
±
l.5
±
7
±
7
12
12
12
3
12
12
2. 6
V
CC
– 2.0
2
5.5
1
6
16.5
15
19
525
+600
6
2
3
1.5
–90
–60
–5
±
2
5
–1
±
1/4
1
–2
±
1/2
2
–1/2
±
1/4
1/2
–3/4
±
1/2
3/4
–1/2
1/2
Monotonic @ All Temperatures
–10
–10
–10
–2
–10
–10
*
*
*
*
*
*
*
*
*
*
*
–4
–1
–2
–1
*
±
2
±
1/4
±
1
±
1/2
±
5
±
5
±
5
±
l
±
5
±
5
10
10
10
2
10
10
*
*
*
*
*
*
*
*
*
*
4
1
2
1
*
*
ppm of FSR
5
/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
kΩ
Volts
Volts
mA
mA
Volts
mA
mA
mW
µA
LSB
LSB
LSB
LSB
dB
dB
8
10
10
*
*
*
µs
µs
nV-sec
dB
kHz
500
–75
70
±
2
±
2
±
2
5
5
5
*
*
*
*
*
*
*
*
*
ppm/%
ppm/%
ppm/%
–2–
REV.
D
AD664
Model
Min
DIGITAL INPUTS
V
IH
V
IL
Data Inputs
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= DGND
CS/DS0/DS1/RST/RD/LS
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= V
LL
MS/TR
12
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= DGND
QS0/QSl/QS2
l2
I
IH
@ V
IN
= V
LL
I
IL
@ V
IN
= DGND
DIGITAL OUTPUTS
V
OL
@ 1.6 mA Sink
V
OH
@ 0.5 mA Source
TEMPERATURE RANGE
JN/JP/KN/KP
AD/AJ/BD/BJ/BE
SD/TD/TE
JN/JP/AD/AJ/SD
Typ
Max
KN/KP/BD/BJ/BE/TD/TE
Min
Typ
Max
Units
2.0
0
–10
–10
–10
–10
–10
–10
–10
–10
±
1
±
1
±
1
±
1
5
–5
5
±
1
0.8
10
10
10
10
10
0
10
10
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Volts
Volts
µA
µA
µA
µA
µA
µA
µA
µA
Volts
Volts
°C
°C
°C
0.4
2.4
*
*
0
– 40
–55
+70
+85
+125
*
*
*
*
*
*
NOTES
1
A minimum power supply of
±12.0
V is required for 0 V to +10 V and
±10
V operation. A minimum power supply of
±11.4
V is required for –5 V to +5 V operation.
2
For V
CC
< +12 V and V
EE
> –12 V. Voltage not to exeeed 10 V maximum.
3
Bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs.
4
Linearity error is defined as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from 0 to F.S. – 1 LSB).
5
FSR means Full-Scale Range and is 20 V for
±
10 V range and 10 V for
±
5 V range.
6
A minimum power supply of
±
12.0 V is required for a 10 V reference voltage.
7
Analog Ground Current is input code dependent.
8
Gain error matching is the largest difference in gain error between any two DACs in one package.
9
Offset error matching is the largest difference in offset error between any two DACs in one package.
10
Bipolar zero error matching is the largest difference in bipolar zero error between any two DACs in one package.
11
Linearity error matching is the difference in the worst ease linearity error between any two DACs in one package.
12
44-pin versions only.
*Specifications same as JN/JP/AD/AJ/SD.
Specifications subject to change without notice.
Specifications shown in
boldface
are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS*
V
LL
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
V
CC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
V
EE
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to 0 V
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V
Reference Input . . . . . . . . . . . . . . . . . . V
REF
≤ ±
10 V and V
REF
≤
(V
CC
– 2 V, V
EE
+ 2 V)
V
CC
to V
EE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +36 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . Indefinite Shorts to
V
CC,
V
LL
, V
EE
and GND
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Unused devices must be stored in conductive foam
or shunts. The protective foam should be discharged to the destination socket before devices are
removed.
WARNING!
ESD SENSITIVE DEVICE
REV.
D
–3–
AD664
Figure 1a. 44-Pin Block Diagram
FUNCTIONAL DESCRIPTION
The AD664 combines four complete 12-bit voltage output D/A
converters with a fast, flexible digital input/output port on one
monolithic chip. It is available in two forms, a 44-pin version
shown in Figure 1a and a 28-pin version shown in Figure 1b.
44-Pin Versions
tions. This register may also be read back to check its contents.
A RESET-TO-ZERO feature allows all DACs to be reset to 0
volts out by strobing a single pin.
Each DAC offers flexibility, accuracy and good dynamic perfor-
mance. The R-2R structure is fabricated from thin-film resistors
which are laser-trimmed to achieve 1/2 LSB linearity and guar-
anteed monotonicity. The output amplifier combines the best
features of the bipolar and MOS devices to achieve good dy-
namic performance and low offset. Settling time is under 10
µs
and each output can drive a 5 mA, 500 pF load. Short-circuit
protection allows indefinite shorts to V
LL
, V
CC
, V
EE
and GND.
The output and span resistor pins are available separately. This
feature allows a user to insert current-boosting elements to in-
crease the drive capability of the system, as well as to overcome
parasitics.
Digital circuitry is implemented in CMOS logic. The fast, low
power, digital interface allows the AD664 to be interfaced with
most microprocessors. Through this interface, the wide variety
of features on each chip may be accessed. For example, the in-
put data for each DAC is programmed by way of 4-, 8-, 12- or
16-bit words. The double-buffered input structure of this latch
allows all four DACs to be updated simultaneously. A readback
feature allows the internal registers to be read back through the
same digital port, as either 4-, 8- or 12-bit words. When dis-
abled, the readback drivers are placed in a high impedance
(tristate) mode. A TRANSPARENT mode allows the input data
to pass straight through both ranks of input registers and appear
at the DAC with a minimum of delay. One D/A may be placed
in the transparent mode at a time, or all four may be made
transparent at once. The MODE SELECT feature allows the
output range and mode of the DACs to be selected via the data
bus inputs. An internal mode select register stores the selec-
Figure 1b. 28-Pin Block Diagram
28-Pin Versions
The 28-pin versions are dedicated versions of the 44-pin
AD664. Each offers a reduced set of features from those offered
in the 44-pin version. This accommodates the reduced number
of package pins available. Data is written and read with 12-bit
words only. Output range and mode select functions are also
not available in 28-pin versions. As an alternative, users specify
either the UNI (unipolar, 0 to V
REF
) models or the BIP (bipolar,
–V
REF
to V
REF
) models depending on the application require-
ments. Finally, the transparent mode is not available on the
28-pin versions.
–4–
REV.
D
AD664
Table I. Transfer Functions
Mode = UNI
Gain = 1
000000000000 = 0 V
100000000000 = V
REF
/2
111111111111 = V
REF
– 1 LSB
000000000000 = 0 V
100000000000 = V
REF
111111111111 = 2
×
V
REF
– 1 LSB
Mode = BIP
000000000000 = – V
REF
/2
100000000000 = 0 V
111111111111 = V
REF
/2 –1 LSB
000000000000 = V
REF
100000000000 = 0 V
111111111111 = +V
REF
– 1 LSB
Gain = 2
DEFINITIONS OF SPECIFICATIONS
LINEARITY ERROR: Analog Devices defines linearity error as
the maximum deviation of the actual, adjusted DAC output
from the ideal analog output (a straight line drawn from 0 to FS
– 1 LSB) for any bit combination. This is also referred to as
relative accuracy. The AD664 is laser-trimmed to typically
maintain linearity errors at less than
±
1/4 LSB.
MONOTONICITY: A DAC is said to be monotonic if the out-
put either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing func-
tion of input. All versions of the AD664 are monotonic over
their full operating temperature range.
DIFFERENTIAL LINEARITY: Monotonic behavior requires
that the differential linearity error be less than 1 LSB both at
25°C as well as over the temperature range of interest. Differen-
tial nonlinearity is the measure of the variation in analog value,
normalized to full scale, associated with a 1 LSB change in digi-
tal input code. For example, for a 10 V full-scale output, a
change of 1 LSB in digital input code should result in a
2.44 mV change in the analog output (V
REF
= 10 V, Gain = 1,
1 LSB = 10 V
×
1/4096 = 2.44 mV). If in actual use, however, a
1 LSB change in the input code results in a change of only
0.61 mV (1/4 LSB) in analog output, the differential non-
linearity error would be –1.83 mV, or –3/4 LSB.
GAIN ERROR: DAC gain error is a measure of the difference
between the output span of an ideal DAC and an actual device.
UNIPOLAR OFFSET ERROR: Unipolar offset error is the dif-
ference between the ideal output (0 V) and the actual output of
a DAC when the input is loaded with all “0s” and the MODE is
unipolar.
BIPOLAR ZERO ERROR: Bipolar zero error is the difference
between the ideal output (0 V) and the actual output of a DAC
when the input code is loaded with the MSB = “1” and the rest
of the bits = “0” and the MODE is bipolar.
SETTLING TIME: Settling time is the time required for the
output to reach and remain within a specified error band about
its final value, measured from the digital input transition.
CROSSTALK: Crosstalk is the change in an output caused by
a change in one or more of the other outputs. It is due to
capacitive and thermal coupling between outputs.
REFERENCE FEEDTHROUGH: The portion of an ac refer-
ence signal that appears at an output when all input bits are low.
Feedthrough is due to capacitive coupling between the reference
input and the output. It is specified in decibels at a particular
frequency.
REFERENCE 3 dB BANDWIDTH: The frequency of the ac
reference input signal at which the amplitude of the full-scale
output response falls 3 dB from the ideal response.
GLITCH IMPULSE: Glitch impulse is an undesired output
voltage transient caused by asymmetrical switching times in the
switches of a DAC. These transients are specified by their net
area (in nV-sec) of the voltage vs. time characteristic.
PIN CONFIGURATIONS
28-Pin DIP Package
44-Pin Package
REV.
D
–5–
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