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PL138-48OC

Description
clock buffer low skew 1:4 lvpecl fanout buffer
Categorylogic    logic   
File Size604KB,20 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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PL138-48OC Overview

clock buffer low skew 1:4 lvpecl fanout buffer

PL138-48OC Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerMicrochip
package instructionGREEN, MO-153AC, TSSOP-20
Reach Compliance Codecompli
Factory Lead Time8 weeks
Other featuresALSO OPERATES AT -2.375 TO -3.8 V SUPPLY
seriesPL138
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length6.5 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)0.79 ns
Same Edge Skew-Max(tskwd)0.037 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.8 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width4.4 mm
minfmax700 MHz
PL138-48
2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer
Features
Four Differential 2.5V/3.3V LVPECL Output Pairs
Output Frequency:
≤800
MHz
Two Selectable Differential Input Pairs
Translates Any Standard Single-Ended or
Differential Input Format to LVPECL Output. It
Can Accept the Following Standard Input Formats
and More:
- LVPECL, LVCMOS, LVDS, HCSL, SSTL,
LVHSTL, CML
Output Skew: 25 ps (typ.)
Part-to-Part Skew: 140 ps (typ.)
Propagation Delay: 1.5 ns (typ.)
Additive Jitter: <100 fs (max.)
Operating Supply Voltage: 2.375V ~ 3.63V
Operating Temperature Range from –40
°
C to
+85
°
C
Package Availability: 16-Pin QFN and 20-Pin
TSSOP
General Description
The PL138-48 is a high performance low-cost 1:4
outputs differential LVPECL fanout buffer.
Microchip’s family of differential LVPECL buffers are
designed to operate from a single power supply of 2.5V
±5% or 3.3V ±10%. The differential input pairs are
designed to accept most standard input signal levels,
using an appropriate resistor bias network, and
produce a high quality set of outputs with the lowest
possible skew on the outputs, which is guaranteed for
part-to-part or lot-to-lot skew.
Designed to fit in a small form-factor package, the
PL138-48 offers up to 800 MHz of output operation with
very low-power consumption and lowest additive jitter
of any comparable device.
Block Diagram
2016 Microchip Technology Inc.
DS20005543B-page 1

PL138-48OC Related Products

PL138-48OC PL138-48QC PL138-48QI
Description clock buffer low skew 1:4 lvpecl fanout buffer IC CLK BUFFER 2:4 1GHZ 16QFN IC CLK BUFFER 2:4 1GHZ 16QFN
type - fanout buffer (allocation), multiplexer fanout buffer (allocation), multiplexer
Number of circuits - 1 1
Ratio - Input:Output - 2:4 2:4
Differential - Input:Output - Yes Yes Yes Yes
enter - CML,HCSL,LVCMOS,LVDS,LVHSTL,LVPECL,SSTL CML,HCSL,LVCMOS,LVDS,LVHSTL,LVPECL,SSTL
output - LVPECL LVPECL
Frequency - maximum - 1GHz 1GHz
Voltage - Power - 2.375 V ~ 3.63 V 2.375 V ~ 3.63 V
Operating temperature - 0°C ~ 70°C -40°C ~ 85°C
Installation type - surface mount surface mount
Package/casing - 16-WFQFN Exposed Pad 16-WFQFN Exposed Pad
Supplier device packaging - 16-QFN(3x3) 16-QFN(3x3)
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