74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop with 30
Ω
termination resistors; 3-state
Rev. 03 — 17 January 2005
Product data sheet
1. General description
The 74LVT162374 is a high performance BiCMOS product designed for V
CC
operation at
3.3 V.
The 74LVT162374 is designed with 30
Ω
series resistance in both the HIGH and LOW
states of the output. This design reduces line noise in applications such as memory
address drivers, clock drivers, and bus receivers/transmitters.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CP), the Q outputs of the flip-flop take on the logic levels
set up at the D inputs.
2. Features
s
s
s
s
s
s
s
s
s
s
s
s
s
16-bit edge-triggered flip-flop
3-state buffers
Output capability: +12 mA and
−12
mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion and extraction permitted
Outputs include series resistance of 30
Ω
making external resistors unnecessary
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection exceeds 500 mA per JESD78
ESD protection:
x
MIL STD 883 method 3015: exceeds 2000 V
x
Machine model: exceeds 200 V
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
3. Quick reference data
Table 1:
Quick reference data
T
amb
= 25
°
C.
Symbol
Parameter
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
V
I
= 0 V or 3.0 V
outputs disabled;
V
O
= 0 V or 3.0 V
outputs disabled;
V
CC
= 3.6 V
Min
-
-
-
-
Typ
3.0
3
9
70
Max
-
-
-
-
Unit
ns
pF
pF
µA
t
PLH
, t
PHL
propagation delay
nCP to nQn
C
I
C
O
I
CC
input capacitance
output capacitance
supply current
4. Ordering information
Table 2:
Ordering information
Package
Temperature range Name
74LVT162374DGG
−40 °C
to +85
°C
74LVT162374DL
−40 °C
to +85
°C
TSSOP48
SSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
plastic shrink small outline package; 48 leads;
body width 7.5 mm
Version
SOT362-1
SOT370-1
Type number
9397 750 14401
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2005
2 of 17
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
5. Functional diagram
47
46
44
43
41
40
38
37
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1CP
1OE
1
1OE
48
1CP
24
2OE
25
2CP
1D0
1D1
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
001aaa254
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1D2
1D3
2
3
5
6
8
9
11
12
1D4
1D5
36
35
33
32
30
29
27
26
1D6
1D7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2D0
2D1
25
24
2CP
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D2
2D3
2D4
2D5
2D6
2D7
13
14
16
17
19
20
22
23
001aac369
Fig 1. Logic symbol
Fig 2. IEC logic symbol
nD0
D
nD1
D
nD2
D
nD3
D
nD4
D
nD5
D
nD6
D
nD7
D
CP
nCP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
001aac371
Fig 3. Logic diagram
9397 750 14401
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2005
3 of 17
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
V
CC
27
Ω
output
27
Ω
001aac372
Fig 4. Output schematic (one output)
6. Pinning information
6.1 Pinning
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48
1CP
47
1D0
46
1D1
45
GND
44
1D2
43
1D3
42
V
CC
41
1D4
40
1D5
39
GND
38
1D6
37
1D7
36
2D0
35
2D1
34
GND
33
2D2
32
2D3
31
V
CC
30
2D4
29
2D5
28
GND
27
2D6
26
2D7
25
2CP
001aac370
GND
10
1Q6
11
1Q7
12
2Q0
13
2Q1
14
GND
15
2Q2
16
2Q3
17
V
CC
18
2Q4
19
2Q5
20
GND
21
2Q6
22
2Q7
23
2OE
24
162374
Fig 5. Pin configuration
9397 750 14401
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2005
4 of 17
Philips Semiconductors
74LVT162374
3.3 V 16-bit edge-triggered D-type flip-flop
6.2 Pin description
Table 3:
Symbol
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
2CP
2D7
2D6
GND
2D5
2D4
V
CC
2D3
2D2
GND
2D1
2D0
1D7
1D6
GND
9397 750 14401
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
Description
output enable input (active LOW)
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
output enable input (active LOW)
clock pulse input (active rising edge)
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
data input
ground (0 V)
data input
data input
data input
data input
ground (0 V)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 — 17 January 2005
5 of 17
Embedded System
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