CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Connecting any terminal to voltages greater than (V+
IN
+ 0.3V) or less than (GND - 0.3V) may cause destructive device latch-up. It is
recommended that no inputs from sources operating on external power supplies be applied prior to ICL7663S power-up.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Input Voltage
Specifications Below Applicable to Both ICL7663S and ICL7663SA, Unless Otherwise Specified. V+
IN
= 9V,
V
OUT
= 5V, T
A
= 25°C, Unless Otherwise Specified. Notes 4, 5. See Test Circuit, Figure 7
SYMBOL
V+
IN
ICL7663S
TEST CONDITIONS
T
A
= 25°C
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
ICL7663SA
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
MIN
1.5
1.6
1.6
1.6
1.6
TYP
-
-
-
-
-
MAX
16
16
16
16
16
UNITS
V
V
V
V
V
Quiescent Current
I
Q
1.4V
≤
V
OUT
≤
8.5V, No Load
V+
IN
= 9V
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
V+
IN
= 16V
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
-
-
-
-
-
-
-
-
10
10
12
12
µA
µA
µA
µA
Reference Voltage
V
SET
I
OUT1
= 100µA, V
OUT
= V
SET
ICL7663S
ICL7663SA
T
A
= 25°C
T
A
= 25°C
1.2
1.275
-
-
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
-
-
-
-
-
V
SHDN
HI: Both V
OUT
Disabled
V
SHDN
LO: Both V
OUT
Enable
1.4
-
-
1.3
1.29
100
100
0.03
0.03
0.01
0.01
±0.01
-
-
0.01
1.4
1.305
-
-
-
0.3
10
10
10
-
0.3
10
V
V
ppm
ppm
%/V
%/V
nA
nA
nA
V
V
nA
Temperature
Coefficient
Line Regulation
∆V
SET
∆T
∆V
SET
V
SET’
∆V
IN
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
2V < V
IN
< 15V
V
SET
Input Current
I
SET
Shutdown Input Current
Shutdown Input Voltage
I
SHDN
V
SHDN
Sense Pin Input Current
I
SENSE
3
FN3180.5
July 21, 2005
ICL7663S
Electrical Specifications
PARAMETER
Sense Pin Input Threshold
Input-Output Saturation
Resistance (Note 3)
Specifications Below Applicable to Both ICL7663S and ICL7663SA, Unless Otherwise Specified. V+
IN
= 9V,
V
OUT
= 5V, T
A
= 25°C, Unless Otherwise Specified. Notes 4, 5. See Test Circuit, Figure 7
(Continued)
SYMBOL
V
CL
R
SAT
V+
IN
= 2V, I
OUT1
= 1mA
V+
IN
= 9V, I
OUT1
= 2mA
V+
IN
= 15V, I
OUT1
= 5mA
Load Regulation
∆V
OUT
∆I
OUT
Available Output Current
(V
OUT2
)
Negative Tempco Output
(Note 4)
Temperature Coefficient
I
OUT2
V
TC
I
TC
∆V
TC
∆T
Minimum Load Current
I
L(MIN)
Includes V
SET
Divider
T
A
= 25°C
0°C < T
A
< 70°C
-25°C < T
A
< 85°C
NOTES:
3. This parameter refers to the saturation resistance of the MOS pass transistor. The minimum input-output voltage differential at low current (under
5mA), can be determined by multiplying the load current (including set resistor current, but not quiescent current) by this resistance.
4. This output has a positive temperature coefficient. Using it in combination with the inverting input of the regulator at V
SET
, a negative
coefficient results in the output voltage. See Figure 9 for details. Pin will not source current.
5. All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V.
6. All significant improvements over the industry standard ICL7663 are highlighted.
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