NB4N11SMNR2G datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Analog mixed-signal IC> Drivers and interfaces> NB4N11SMNR2G

NB4N11SMNR2G: Descriptionclock buffer lvds fanout buff/ trans; CategoryAnalog mixed-signal IC Drivers and interfaces; File Size105KB，10 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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clock buffer lvds fanout buff/ trans

NB4N11SMNR2G Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	ON Semiconductor
Parts packaging code	QFN
package instruction	HVQCCN,
Contacts	16
Reach Compliance Code	compli
ECCN code	EAR99
Factory Lead Time	1 week
Other features	CML, LVCMOS, LVTTL OR LVDS TO LVDS TRANSLATION ALSO POSSIBLE
maximum delay	0.47 ns
Interface integrated circuit type	PECL TO LVDS TRANSLATOR
JESD-30 code	S-XQCC-N16
JESD-609 code	e4
length	3 mm
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output latch or register	NONE
Output polarity	COMPLEMENTARY
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	3 mm

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NB4N11S

3.3 V 1:2 AnyLevel™ Input

to LVDS Fanout Buffer /

Translator

The NB4N11S is a differential 1:2 Clock or Data Receiver and will

accept AnyLevel

input signals: LVPECL, CML, LVCMOS,

LVTTL, or LVDS. These signals will be translated to LVDS and two

identical copies of Clock or Data will be distributed, operating up to

2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N11S is ideal for

SONET, GigE, Fiber Channel, Backplane and other Clock or Data

distribution applications.

The NB4N11S has a wide input common mode range from

GND + 50 mV to V

− 50 mV. Combined with the 50

internal

termination resistors at the inputs, the NB4N11S is ideal for

translating a variety of differential or single−ended Clock or Data

signals to 350 mV typical LVDS output levels.

The NB4N11S is functionally equivalent to the EP11, LVEP11,

SG11 or 7L11M devices and is offered in a small 3 mm X 3 mm

16−QFN package. Application notes, models, and support

documentation are available at www.onsemi.com.

Features

http://onsemi.com

MARKING

DIAGRAM*

QFN−16

MN SUFFIX

CASE 485G

NB4N

11S

ALYW

= Assembly Location

= Wafer Lot

= Year

= Work Week

•

Maximum Input Clock Frequency > 2.0 GHz

Maximum Input Data Rate > 2.5 Gb/s

1 ps Maximum of RMS Clock Jitter

Typically 10 ps of Data Dependent Jitter

380 ps Typical Propagation Delay

120 ps Typical Rise and Fall Times

Functionally Compatible with Existing 3.3 V LVEL, LVEP, EP, and

SG Devices

*For additional marking information, refer to

Application Note AND8002/D.

VOLTAGE (130 mV/div)

Device DDJ = 10 ps

Figure 1. Logic Diagram

TIME (58 ps/div)

Figure 2. Typical Output Waveform at 2.488 Gb/s with

PRBS 2

23−1

INPP

= 400 mV; Input Signal DDJ = 14 ps)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

Semiconductor Components Industries, LLC, 2005

December, 2005 − Rev. 0

Publication Order Number:

NB4N11S/D

NB4N11SMNR2G Related Products

	NB4N11SMNR2G	NB4N11SMNG
Description	clock buffer lvds fanout buff/ trans	IC buffer/xlator lvds 16-qfn
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	ON Semiconductor	ON Semiconductor
Parts packaging code	QFN	QFN
package instruction	HVQCCN,	HVQCCN,
Contacts	16	16
Reach Compliance Code	compli	compliant
ECCN code	EAR99	EAR99
Factory Lead Time	1 week	1 week
Other features	CML, LVCMOS, LVTTL OR LVDS TO LVDS TRANSLATION ALSO POSSIBLE	CML, LVCMOS, LVTTL OR LVDS TO LVDS TRANSLATION ALSO POSSIBLE
maximum delay	0.47 ns	0.47 ns
Interface integrated circuit type	PECL TO LVDS TRANSLATOR	PECL TO LVDS TRANSLATOR
JESD-30 code	S-XQCC-N16	S-XQCC-N16
length	3 mm	3 mm
Humidity sensitivity level	1	1
Number of digits	1	1
Number of functions	1	1
Number of terminals	16	16
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output latch or register	NONE	NONE
Output polarity	COMPLEMENTARY	COMPLEMENTARY
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260	260
Certification status	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Gold/Palladium (Ni/Au/Pd)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	40	40
width	3 mm	3 mm

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