DS33X11+ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> DS33X11+

DS33X11+: Descriptionnetwork controller & processor ics ethernet over pdh mapping devices; CategoryWireless rf/communication Telecom circuit; File Size3MB，375 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

Download Datasheet Parametric Compare View All

DS33X11+ Overview

network controller & processor ics ethernet over pdh mapping devices

DS33X11+ Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	BGA
package instruction	LFBGA,
Contacts	144
Reach Compliance Code	compli
ECCN code	EAR99
Factory Lead Time	11 weeks
JESD-30 code	S-PBGA-B144
JESD-609 code	e1
length	10 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	144
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Nominal supply voltage	1.8 V
surface mount	YES
Telecom integrated circuit types	SUPPORT CIRCUIT
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm

Preview

Download Datasheet

View All

Rev: 063008

DS33X162/DS33X161/DS33X82/DS33X81/

DS33X42/DS33X41/DS33X11/DS33W41/DS33W11

Ethernet Over PDH Mapping Devices

General Description

The DS33X162 family of semiconductor devices

extend 10/100/1000Mbps Ethernet LAN segments by

encapsulating MAC frames in GFP-F, HDLC, cHDLC,

or X.86 (LAPS) for transmission over PDH/TDM data

streams. The devices support the Ethernet over PDH

(EoPDH) standards for the delivery of Ethernet

Access Services, including eLAN, eLINE, and VLAN.

The multiport devices support VCAT/LCAS for

dynamic link aggregation. The serial links support

bidirectional synchronous interconnect up to 52Mbps

over xDSL, T1/E1/J1, T3/E3, or V.35/Optical.

The devices perform store-and-forward of frames

with Ethernet traffic conditioning and bridging

functions at wire speed. The programmability of

classification, priority queuing, encapsulation, and

bundling allows great flexibility in providing various

Ethernet services. OAM flows can be extracted and

inserted by an external processor to manage the

Ethernet service.

The voice ports of the DS33W41 and DS33W11

easily connect to external codecs for integrated voice

and data service applications.

♦

Features

10/100/1000 IEEE 802.3 MAC (MII/RMII/GMII)

with Autonegotiation and Flow Control

GFP-F/LAPS/HDLC/cHDLC Encapsulation

VCAT/LCAS Link Aggregation for Up to 16

Links

Supports Up to 200ms Differential Delay

Quality of Service (QoS) Support

VLAN, Q-in-Q, 802.1p, and DSCP Support

Ethernet Bridging and Filtering

Add/Drop OAM Frames from

μP

Interface

Traffic Shaping Through CIR/CBS Policing

External 256Mb, 125MHz DDR SDRAM Buffer

Parallel and SPI™ Microprocessor Interfaces

1.8V, 2.5V, 3.3V Supplies

IEEE 1149.1 JTAG Support

Features continued in Section

Ordering Information

PART

DS33X162+

DS33X161+

DS33X82+

DS33X81+

DS33X42+

DS33X41+

DS33X11+

DS33W41+

DS33W11+

TDM

PORTS

ETHERNET

VOICE

PIN-

PACKAGE

256 CSBGA

144 CSBGA

256 CSBGA

Applications

Bonded Transparent LAN Service

LAN Extension

Ethernet Delivery Over T1/E1/J1, T3/E3,

OC-1/EC-1, G.SHDSL, or HDSL2/4

Functional Diagram

PROCESSOR

8-BIT & SPI

μP

INTERFACE

TRAFFIC

MGMT

TDM LIU/

FRAMER

VOICE PORT

BUFFER MANAGER

SDRAM CONTROLLER

DDR SDRAM

BRIDGING

MACs

WAN

SERIAL

PORTS

GFP/

LAPS/

HDLC

CLAD

QoS

POLICY

ENET

PHYs

Note:

All devices are specified over the -40

C to +85

C industrial

operating temperature range.

+Denotes

a lead-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

DS33X162

Maxim Integrated Products

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of

any device may be simultaneously available through various sales channels. For information about device errata, go to:

www.maxim-ic.com/errata.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or

visit Maxim’s website at www.maxim-ic.com.

_________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11

Table of Contents

2.1

2.2

2.3

2.4

2.5

2.6

2.7

DETAILED DESCRIPTION .............................................................................................................. 9

FEATURE HIGHLIGHTS................................................................................................................ 10

ENERAL

...................................................................................................................................... 10

VCAT/LCAS L

INK

GGREGATION

NVERSE

ULTIPLEXING

) ..........................................................10

HDLC........................................................................................................................................... 10

cHDLC.................................................................................................................................................. 10

2.3.1

GFP-F.......................................................................................................................................... 11

X.86 S

UPPORT

.............................................................................................................................11

DDR SDRAM I

NTERFACE

.............................................................................................................11

MAC I

NTERFACES

.........................................................................................................................11

Ethernet Bridging for 10/100 ................................................................................................................ 12

Ethernet Traffic Classification .............................................................................................................. 12

Ethernet Bandwidth Policing ................................................................................................................ 12

Ethernet Traffic Scheduling.................................................................................................................. 12

Connection Endpoints .......................................................................................................................... 12

Virtual Connection................................................................................................................................ 12

Connection and Aggregation ............................................................................................................... 12

Ethernet Control Frame Processing..................................................................................................... 12

Q-in-Q .................................................................................................................................................. 12

Voice Ports........................................................................................................................................... 13

2.7.1

2.7.2

2.7.3

2.7.4

2.7.5

2.7.6

2.7.7

2.7.8

2.7.9

2.8

ERIAL

ORTS

..............................................................................................................................13

2.8.1

2.9 M

ICROPROCESSOR

NTERFACE

......................................................................................................13

2.10

LAVE

ERIAL

ERIPHERAL

NTERFACE

(SPI) F

EATURES

............................................................13

2.11

EST AND

IAGNOSTICS

.............................................................................................................13

2.12

PECIFICATIONS

OMPLIANCE

....................................................................................................13

5.1

5.2

5.3

5.4

5.5

5.6

7.1

8.1

APPLICABLE EQUIPMENT TYPES..............................................................................................14

ACRONYMS & GLOSSARY ..........................................................................................................17

DESIGNING WITH THE DS33X162 FAMILY OF DEVICES..........................................................18

DENTIFICATION OF

PPLICATION

EQUIREMENTS

..........................................................................18

EVICE

ELECTION

.......................................................................................................................18

NCILLARY

EVICE

ELECTION

......................................................................................................19

IRCUIT

ESIGN

............................................................................................................................19

OARD

AYOUT

.............................................................................................................................19

OFTWARE

EVELOPMENT

............................................................................................................19

BLOCK DIAGRAMS ...................................................................................................................... 20

PIN DESCRIPTIONS ...................................................................................................................... 21

UNCTIONAL

ESCRIPTION

......................................................................................................21

FUNCTIONAL DESCRIPTION .......................................................................................................34

ARALLEL

ROCESSOR

NTERFACE

................................................................................................35

Read-Write/Data Strobe Modes........................................................................................................... 35

Clear on Read ...................................................................................................................................... 35

Interrupt and Pin Modes....................................................................................................................... 35

Multiplexed Bus Operation................................................................................................................... 35

8.1.1

8.1.2

8.1.3

8.1.4

8.2

8.3

SPI S

ERIAL

ROCESSOR

NTERFACE

.............................................................................................36

LOCK

TRUCTURE

.......................................................................................................................37

Serial Interface Clock Modes ............................................................................................................... 39

Ethernet Interface Clock Modes........................................................................................................... 39

2 of 375

8.3.1

8.3.2

Rev: 063008

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11

8.4

8.5

8.6

8.7

8.8

8.9

ESETS AND

-P

OWER

ODES

................................................................................................39

NITIALIZATION AND

ONFIGURATION

..............................................................................................41

LOBAL

ESOURCES

....................................................................................................................41

-P

ORT

ESOURCES

................................................................................................................41

EVICE

NTERRUPTS

.....................................................................................................................41

ORWARDING

ODES AND

WAN C

ONNECTIONS

............................................................................43

Forwarding Modes ............................................................................................................................... 43

WAN Connections................................................................................................................................ 49

Queue Configuration ............................................................................................................................ 50

8.9.1

8.9.2

8.9.3

8.10

8.11

8.11.1

ANDWIDTH

APABILITIES

HROUGHPUT

)..................................................................................51

ERIAL

(WAN)........................................................................................................................... 52

Voice Support (DS33W11 and DW33W41 Only)................................................................................. 52

8.12

8.12.1

8.12.2

8.12.3

8.12.4

INK

GGREGATION AND

INK

APACITY

DJUSTMENT

(VCAT/LCAS) ........................................53

VCAT/LCAS Control Frame for T3/E3 ................................................................................................. 54

VCAT/LCAS Configuration and Operation........................................................................................... 55

Link Capacity Adjustment Scheme (LCAS) ......................................................................................... 56

Alarms and Conditions related to VCAT/LCAS.................................................................................... 57

8.13

8.14

8.14.1

8.14.2

RBITER

UFFER

ANAGER

.......................................................................................................57

LOW

ONTROL

.........................................................................................................................58

Full Duplex Flow control....................................................................................................................... 59

Half Duplex Flow control ...................................................................................................................... 59

8.15

8.15.1

8.15.2

8.15.3

8.15.4

THERNET

NTERFACES

.............................................................................................................60

GMII Mode ........................................................................................................................................... 62

MII Mode .............................................................................................................................................. 63

DTE and DCE Mode ............................................................................................................................ 65

RMII Mode............................................................................................................................................ 66

8.16

8.16.1

8.16.2

8.16.3

8.16.4

8.16.5

8.16.6

UALITY OF

ERVICE

S) F

EATURES

.....................................................................................67

VLAN Forwarding by VID (IEEE 802.1q) ............................................................................................. 67

Programming the VLAN ID Table ........................................................................................................ 68

Priority Coding with VLAN Tags (IEEE 802.1p)................................................................................... 69

Priority Coding with Multiple (Q-in-Q) VLAN Tags............................................................................... 70

Priority Coding with DSCP ................................................................................................................... 71

Programming the Priority Table ........................................................................................................... 72

8.17

8.17.1

8.17.2

8.17.3

8.17.4

8.17.5

8.17.6

OAM

SUPPORT WITH

RAME

RAPPING

, E

XTRACTION

AND

NSERTION

.......................................74

Frame Trapping.................................................................................................................................... 76

Frame Extraction and Frame Insertion ................................................................................................ 77

OAM by Ethernet Destination Address (DA)........................................................................................ 78

OAM by IP Address.............................................................................................................................. 78

OAM by VLAN Tag............................................................................................................................... 78

SNMP Support ..................................................................................................................................... 78

8.18

8.18.1

RIDGING AND

ILTERING

...........................................................................................................79

Bridge Filter Table Reset ..................................................................................................................... 79

8.19

8.19.1

8.19.2

8.19.3

THERNET

MAC ........................................................................................................................80

PHY MII Management Block and MDIO Interface ............................................................................... 83

Ethernet MAC Management Counters for RFC2819 RMON ............................................................... 84

Programmable Ethernet Destination Address Filtering........................................................................ 85

8.20

8.20.1

8.20.2

8.20.3

8.20.4

8.20.5

8.20.6

THERNET

RAME

NCAPSULATION

...........................................................................................86

Transmit Packet Processor (Encapsulator) ......................................................................................... 86

Receive Packet Processor (Decapsulator) .......................................................................................... 87

GFP-F Encapsulation and Decapsulation............................................................................................ 89

X.86 Encoding and Decoding .............................................................................................................. 94

HDLC Encoding and Decoding ............................................................................................................ 96

cHDLC Encoding And Decoding.......................................................................................................... 98

8.21

CIR/CBS C

ONTROLLER

.............................................................................................................99

APPLICATIONS INFORMATION.................................................................................................101

3 of 375

Rev: 063008

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11

13.2.2

13.2.3

13.2.4

13.2.5

13.2.6

BYPASS............................................................................................................................................. 367

EXTEST ............................................................................................................................................. 367

CLAMP............................................................................................................................................... 367

HIGHZ ................................................................................................................................................ 367

IDCODE ............................................................................................................................................. 367

13.3

13.4

13.4.1

13.4.2

13.4.3

JTAG ID C

ODES

......................................................................................................................368

EST

EGISTERS

.....................................................................................................................368

Boundary Scan Register .................................................................................................................... 368

Bypass Register ................................................................................................................................. 368

Identification Register......................................................................................................................... 368

13.5

14.

14.1

14.2

14.3

15.

15.1

15.2

16.

JTAG F

UNCTIONAL

IMING

......................................................................................................369

DS33X162/X161/X82/X81/X42/X41 P

ONFIGURATION

—256-B

ALL

CSBGA....................... 370

DS33W41/DS33W11 P

ONFIGURATION

—256-B

ALL

CSBGA .............................................371

DS33X11 P

ONFIGURATION

—144-B

ALL

CSBGA................................................................372

256-B

ALL

CSBGA, 17

MM X

(56-G6017-001) .................................................................373

144-B

ALL

CSBGA, 10

MM X

(56-G6008-003) .................................................................374

PIN CONFIGURATION ................................................................................................................ 370

PACKAGE INFORMATION .........................................................................................................373

DOCUMENT REVISION HISTORY ..............................................................................................375

Rev: 063008

5 of 375

DS33X11+ Related Products

	DS33X11+	DS33W41+	DS33W11+	DS33X41+	DS33X82+	DS33X162+
Description	network controller & processor ics ethernet over pdh mapping devices	network controller & processor ics ethernet over pdh mapping devices	network controller & processor ics ethernet over pdh mapping devices	network controller & processor ics ethernet over pdh mapping devices	network controller & processor ics ethernet over pdh mapping devices	network controller & processor ics ethernet over pdh mapping devices
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to
Maker	Maxim	Maxim	Maxim	Maxim	Maxim	Maxim
Parts packaging code	BGA	BGA	BGA	BGA	BGA	BGA
package instruction	LFBGA,	17 X 17 MM, 1 MM PITCH, LEAD FREE, CSBGA-256	BGA,	BGA,	BGA,	17 X 17 MM, 1 MM PITCH, LEAD FREE, CSBGA-256
Contacts	144	256	256	256	256	256
Reach Compliance Code	compli	compli	compli	compli	compli	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
Factory Lead Time	11 weeks	1 week	11 weeks	1 week	12 weeks	1 week
JESD-30 code	S-PBGA-B144	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256	S-PBGA-B256
JESD-609 code	e1	e1	e1	e1	e1	e1
length	10 mm	17 mm	17 mm	17 mm	17 mm	17 mm
Humidity sensitivity level	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1
Number of terminals	144	256	256	256	256	256
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	BGA	BGA	BGA	BGA	BGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.5 mm	1.77 mm	1.77 mm	1.77 mm	1.77 mm	1.77 mm
Nominal supply voltage	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES	YES
Telecom integrated circuit types	SUPPORT CIRCUIT	SUPPORT CIRCUIT	SUPPORT CIRCUIT	SUPPORT CIRCUIT	SUPPORT CIRCUIT	SUPPORT CIRCUIT
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	30	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	10 mm	17 mm	17 mm	17 mm	17 mm	17 mm

Recommended Resources

KONE 3000 elevator safety circuit circuit

Sign indicator circuit

Motor Y-△ starting circuit

M131W universal cylindrical grinder electrical schematic circuit

Basic application circuit diagram of adjustable LT108X

555 limited time warning circuit

Keysight Material Dielectric Constant Test Method - Just Read the Content: Industries need to have a very clear understanding of the materials they use in order to reduce the time spent in the design, factory inspection, process testing and quality assurance stages. Each mat...; btty038 RF/Wirelessly

This week's highlights: [b][url=https://e2echina.ti.com/blogs_/b/power_house/archive/2018/04/09/52819]Texas Instruments helps Bitcoin mining machine power supply[/url][/b][font=微软雅黑][size=3][color=#000000] [/color][/size][/f...; 橙色凯 Analogue and Mixed Signal

EEWORLD University Hall----16-bit timer Timer_A: 16-bit timer Timer_A : https://training.eeworld.com.cn/course/360...; dongcuipin MCU

Implementation of constant current power supply for LED lighting: 1. Comparison and selection of solutions 1 Circuit topology scheme Scheme 1: The power factor correction circuit adopts the flyback topology structure. The advantage is that the power factor correctio...; 404846547 LED Zone

Sound pressure, sound intensity and sound power: Sound pressure, sound intensity and sound powerWe all know that the three parameters that describe sound are sound pressure, sound intensity and sound power. There is a certain relationship between th...; QWE4562009 Test/Measurement

Easy Power Learning Experience: [b]Nano Module Introduction: [/b]The new SIMPLE SWITCHER Easy Power Nano Module is ideal for space-constrained applications, expanding the product portfolio and capabilities of the smallest 1A package...; amww Analogue and Mixed Signal

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components