256k
×
16-Bit EDO-DRAM
HYB 514175BJ-50/-55/-60
Advanced Information
•
•
•
•
262 144 words by 16-bit organization
0 to 70
°C
operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
55 ns (-55 version)
60 ns (-60 version)
CAS access time:
13 ns (-50 & -55 version)
15 ns (-60 version)
Cycle time:
89 ns (-50 version)
94 ns (-55 version)
104 ns (-60 version)
Hyper page mode (EDO) cycle time
20 ns (-50 & -55 version)
25 ns (-60 version)
High data rate
50 MHz (-50 & -55 version)
40 MHz (-60 version)
Single + 5 V (± 10 %) supply with a built-in
V
BB
generator
• Low Power dissipation
max. 1100 mW active (-50 version)
max. 1045 mW active (-55 version)
max. 935 mW active (-60 version)
• Standby power dissipation
11 mW standby (TTL)
5.5 mW max. standby (CMOS)
• Output unlatched at cycle end allows
two-dimensional chip selection
• Read, write, read-modify write,
CAS-before-RAS refresh, RAS-only
refresh, hidden-refresh and hyper page
(EDO) mode capability
• 2 CAS/1 WE control
• All inputs and outputs TTL-compatible
• 512 refresh cycles/16 ms
• Plastic Packages:
P-SOJ-40-1 400 mil width
•
•
•
•
•
Semiconductor Group
1
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k
×
16 EDO-DRAM
The HYB 514175BJ is the new generation dynamic RAM organized as 262 144 words by 16-bit.
The HYB 514175BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to
provide wide operation margins, both internally and for the system user. Multiplexed address inputs
permit the HYB 514175BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package.
This package size provides high system bit densities and is compatible with commonly used
automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %)
power supply, direct interfacing with high performance logic device families such as Schottky TTL.
Ordering Information
Type
HYB 514175BJ-50
HYB 514175BJ-55
HYB 514175BJ-60
Truth Table
RAS
H
L
L
L
L
L
L
L
L
LCAS
H
H
L
H
L
L
H
L
L
UCAS
H
H
H
L
L
H
L
L
L
WE
H
H
H
H
H
L
L
L
H
OE
H
H
L
L
L
H
H
H
H
I/O1 - I/O8
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
I/O9 - I/O16
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Operation
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
−
Ordering Code
Q67100-Q2072
Q67100-Q2100
Q67100-Q2073
Package
P-SOJ-40-1 400 mil
P-SOJ-40-1 400 mil
P-SOJ-40-1 400 mil
Description
50 ns 256k
×
16 EDO-DRAM
55 ns 256k
×
16 EDO-DRAM
60 ns 256k
×
16 EDO-DRAM
Pin Names
A0 - A8
RAS
UCAS, LCAS
WE
OE
I/O1 -I/O16
Address Inputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Output Enable
Data Input/Output
Power Supply (+ 5 V)
Ground (0 V)
No Connection
V
CC
V
SS
N.C.
Semiconductor Group
2
1998-10-01
HYB 514175BJ-50/-55/-60
256k
×
16 EDO-DRAM
P-SOJ-40-1
V
CC
I/O1
I/O2
I/O3
I/O4
V
CC
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS
N.C.
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
V
SS
39 I/O16
38 I/O15
37 I/O14
36 I/O13
35
V
SS
34 I/O12
33 I/O11
32 I/O10
31 I/O9
30 N.C.
29 LCAS
28 UCAS
27 OE
26 A8
25 A7
24 A6
23 A5
22 A4
21
V
SS
SPP02811
Pin Configuration
(top view)
Semiconductor Group
3
1998-10-01
HYB 514175BJ/BJL-50/-55/-60
256k
×
16 EDO-DRAM
I/O1 I/O2 . . . I/O16
. .
.
.
Data In
Buffer
WE
UCAS
LCAS
&
16
Data Out
Buffer
16
OE
No.2 Clock
Generator
9
Column
Address
Buffers (9)
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
9
Refresh
Counter (9)
9
Row
Address
Buffers (9)
9
Row
Decoder
.
.
.
512
.
.
.
Refresh
Controller
Column
Decoder
Sense Amplifier
I/O Gating
512
x 16
16
Memory Array
512 x 512 x 16
.
.
.
.
.
.
RAS
No.1 Clock
Generator
Substrate Bias
Generator
V
CC
V
SS
SPB02827
Block Diagram
Semiconductor Group
4
1998-10-01
HYB 514175BJ-50/-55/-60
256k
×
16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ....................................................................................... 0 to + 70
°C
Storage temperature range.................................................................................... – 55 to + 150
°C
Input/output voltage ....................................................................................................... – 1 to + 6 V
Power supply voltage..................................................................................................... – 1 to + 6 V
Data out current (short circuit) ............................................................................................... 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
DC Characteristics
T
A
= 0 to 70
°C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5.0 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current, any input
(0 V <
V
IN
< 7 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V <
V
OUT
<
V
CC
)
Average
V
CC
supply current
-50 version
-55 version
-60 version
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
IH
)
Average
V
CC
supply current during
RAS-only refresh cycles
-50 version
-55 version
-60 version
Average
V
CC
supply current during
hyper page mode (EDO) operation
-50 version
-55 version
-60 version
Symbol
Limit Values
min.
max.
0.8
–
0.4
10
10
2.4
– 1.0
2.4
–
– 10
– 10
–
200
190
170
mA
2, 3, 4
Unit Test
Condition
1
1
1
1
1
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
V
CC
+ 0.5 V
V
V
V
µA
µA
1
I
CC2
I
CC3
–
–
2
mA
200
190
170
mA
2, 4
I
CC4
–
190
180
170
mA
2, 3, 4
Semiconductor Group
5
1998-10-01
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