2M
×
8 - Bit Dynamic RAM
2k Refresh
(Fast Page Mode)
Advanced Information
• 2 097 152 words by 8-bit organization
• 0 to 70
°C
operating temperature
• Fast Page Mode operation
• Performance:
-50
-60
60
15
30
104
40
ns
ns
ns
ns
ns
HYB 5117800/BSJ-50/-60
HYB 3117800BSJ-50/-60
t
RAC
t
CAC
t
AA
t
RC
t
PC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
50
13
25
84
35
• Power dissipation:
HYB5117800
-50
Power Supply
Active
TTL Standby
CMOS Standby
440
-60
5
±
10%
385
11
5.5
HYB3117800
-50
288
-60
3.3
±
0.3 V
252
7.2
3.6
mW
mW
mW
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• 2048 refresh cycles / 32 ms (2k-refresh)
• Plastic Package:
P-SOJ-28-3 400 mil
Semiconductor Group
1
1998-10-01
HYB 5(3)117800/BSJ-50/-60
2M
×
8 DRAM
The HYB 5(3)117800 are 16 MBit dynamic RAMs based on the die revisions “G” & “F” and
organized as 2 097 152 words by 8-bits. The HYB 5(3)117800 utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117800 to
be packaged in a standard SOJ-28 plastic package. Package with 400 mil width are available.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment.
Ordering Information
Type
HYB 5117800BSJ-50
HYB 5117800BSJ-60
HYB 3117800BSJ-50
HYB 3117800BSJ-60
Ordering Code
Q67100-Q1092
Q67100-Q1093
on request
on request
Package
Descriptions
P-SOJ-28-3 400 mil 5 V 50 ns FPM-DRAM
P-SOJ-28-3 400 mil 5 V 60 ns FPM-DRAM
P-SOJ-28-3 400 mil 3.3 V 50 ns FPM-DRAM
P-SOJ-28-3 400 mil 3.3 V 60 ns FPM-DRAM
P-SOJ-28 400 mil
V
CC
I/O1
I/O2
I/O3
I/O4
WE
RAS
N.C.
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
V
SS
27 I/O8
26 I/O7
25 I/O6
24 I/O5
23 CAS
22 OE
21 A9
20 A8
19 A7
18 A6
17 A5
16 A4
15
V
SS
SPP02803
Pin Names and Configuration
A0 - A10
A0 - A9
RAS
OE
I/O1 - I/O8
CAS
WE
Row Address Inputs
Column Address Inputs
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply
+ 5 V for HYB 5117800
+ 3.3 V for HYB 3117800
Ground (0 V)
Not Connected
V
CC
V
SS
N.C.
Semiconductor Group
2
1998-10-01
HYB 5(3)117800/BSJ-50/-60
2M
×
8 DRAM
I/O1 I/O2
I/O8
Data IN
Buffer
WE
CAS
8
No.2 Clock
Generator
&
Data OUT
Buffer
OE
8
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Column
Address
Buffers (10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
4
Refresh
Counter (11)
11
11
Row
Address
Buffers (11)
11
Row
Decoder
2048
1024
x8
Memory Array
2048 x 1024 x 8
RAS
No.1 Clock
Generator
Voltage Down
Generator
SPB03456
V
CC
V
CC
(internal)
Block Diagram
Semiconductor Group
3
1998-10-01
HYB 5(3)117800/BSJ-50/-60
2M
×
8 DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................... 0 to 70
°C
Storage temperature range........................................................................................ – 55 to 150
°C
Input/output voltage (5 V versions) ................................................... – 0.5 to min (
V
CC
+ 0.5, 7.0) V
Input/output voltage (3.3 V versions) ................................................ – 0.5 to min (
V
CC
+ 0.5, 4.6) V
Power supply voltage (5 V versions) ....................................................................... – 1.0 V to 7.0 V
Power supply voltage (3.3 V versions) .................................................................... – 1.0 V to 4.6 V
Power dissipation (5 V versions) ............................................................................................. 1.0 W
Power dissipation (3.3 V versions) .......................................................................................... 0.5 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70
°C,
V
SS
= 0 V,
t
T
= 2 ns
Parameter
5 V Versions
Power supply voltage
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
3.3 V Versions
Power supply voltage
Input high voltage
Input low voltage
TTL Output high voltage (
I
OUT
= – 2 mA)
TTL Output low voltage (
I
OUT
= 2 mA)
CMOS Output high voltage (
I
OUT
= – 100
µA)
CMOS Output low voltage (
I
OUT
= 100
µA)
Symbol
Limit Values
min.
max.
5.5
0.8
–
0.4
3.6
0.8
–
0.4
0.2
Unit Test
Condition
V
CC
V
IH
V
IL
V
OH
V
OL
V
CC
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
4.5
2.4
– 0.5
2.4
–
3.0
2.0
– 0.5
2.4
–
–
V
1
1
1
1
V
CC
+ 0.5 V
V
V
V
V
V
CC
+ 0.5 V
V
V
V
V
V
1
1
1
1
V
CC
– 0.2 –
Semiconductor Group
4
1998-10-01
HYB 5(3)117800/BSJ-50/-60
2M
×
8 DRAM
DC Characteristics
(cont’d)
T
A
= 0 to 70
°C,
V
SS
= 0 V,
t
T
= 2 ns
Parameter
Common Parameters
Input leakage current
(0 V
≤
V
IH
≤
V
CC
+ 0.3 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
V
CC
+ 0.3 V)
Average
V
CC
supply current
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC MIN.
)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
Average
V
CC
supply current, during RAS-only
I
CC3
refresh cycles
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC MIN.
)
Average
V
CC
supply current,
during fast page mode
Symbol
Limit Values
min.
max.
10
10
Unit Test
Condition
I
I(L)
I
O(L)
I
CC1
– 10
– 10
µA
µA
1
1
–
–
–
–
–
80
70
2
80
70
mA
mA
mA
mA
mA
2, 3, 4
2, 3, 4
–
2, 4
2, 4
I
CC4
–
–
25
20
1
mA
mA
mA
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
t
PC
=
t
PC MIN.
)
2, 3,) 4
2, 3, 4
Standby
V
CC
supply current
(RAS = CAS =
V
CC
– 0.2 V)
I
CC5
–
1
Average
V
CC
supply current, during CAS-
I
CC6
before-RAS refresh mode
-50 ns version
-60 ns version
(RAS, CAS cycling:
t
RC
=
t
RC MIN.
)
Capacitance
T
A
= 0 to 70
°C,
V
CC
= 5 V
±
10 %,
f
= 1 MHz
Parameter
Input capacitance (A0 to A10)
Input capacitance (RAS, CAS, WE, OE)
I/O capacitance (I/O1 to I/O8)
–
–
80
70
mA
mA
2, 4
2,) 4
Symbol
Limit Values
min.
max.
5
7
7
–
–
–
Unit
pF
pF
pF
C
I1
C
I2
C
IO
Semiconductor Group
5
1998-10-01
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