256K x 16-Bit EDO-Dynamic RAM
HYB 514265BJ-400/40/-45/-50
HYB 314265BJ(L)-45/-50
Preliminary Information
•
•
•
•
262 144 words by 16-bit organization
0 to 70
°C
operating temperature
EDO - Hyper Page Mode
Performance:
-400
-40
69
40
10
20
15
66
-45
79
45
12
22
18
55
-50
89
50
13
25
20
50
ns
ns
ns
ns
ns
MHz
•
Power Supply:
HYB 514265BJ-400
HYB 514265BJ-40
HYB 514265BJ-45
HYB 514265BJ-50
+5 V
+5 V
+5 V
+5 V
±5%
±10%
±10%
±10%
HYB 314265BJ(L)-45 +3.3 V
±0.3
V
HYB 314265BJ(L)-50 +3.3 V
±0.3
V
Read, write, read-modify-write, CAS -before
RAS refresh, RAS only refresh, hidden refresh
mode
•
Low Power Version (L) with Self Refresh
and 250
µA
self refresh current
•
•
t
rc
t
rac
t
cac
t
aa
t
hpc
t
hpc
•
69
40
10
20
12,5
80
2 CAS / 1 WE control
All inputs and outputs TTL-compatible
512 refresh cycles / 16 ms
512 refresh cycles / 128 ms (L-version)
Plastic Packages: P-SOJ-40-3 400 mil width
Low Power dissipation
- Active(max.):
120mA / 120mA / 105mA / 95 mA
- Standby : TTL Inputs (max.)
2.0 mA
- Standby: CMOS Inputs (max.) 1.0 mA
- Standby (L-version)
200
µA
•
•
•
The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by
16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process
as well as advanced circuit techniques to provide wide operation margins, both internally and for the
system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a
standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit
densities and is compatible with commonly used automatic testing and insertion equipment.
The HYB314265BJL parts have a very low power “sleep mode“ supported by Self Refresh.
Semiconductor Group
1
6.96
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Ordering Information
Type
5 V versions:
HYB 514265BJ-400
HYB 514265BJ-40
HYB 514265BJ-45
HYB 514265BJ-50
3.3 V versions:
HYB 314265BJ-45
HYB 314265BJ-50
HYB 314265BJL-45
HYB 314265BJL-50
on request
on request
on request
on request
P-SOJ-40-3
P-SOJ-40-3
P-SOJ-40-3
P-SOJ-40-3
3.3 V 45 ns 256 K x 16 EDO- DRAM
3.3 V 50 ns 256 K x 16 EDO- DRAM
3.3 V Low Power 45 ns 256 K x 16 EDO- DRAM
3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM
Q67100-3033
Q67100-3039
Q67100-3035
Q67100-3036
P-SOJ-40-3
P-SOJ-40-3
P-SOJ-40-3
P-SOJ-40-3
5 V 40 ns 256 K x 16 EDO-DRAM
5 V 40 ns 256 K x 16 EDO-DRAM
5 V 45 ns 256 K x 16 EDO-DRAM
5 V 50 ns 256 K x 16 EDO-DRAM
Ordering
Code
Package
Description
Truth Table
RAS
H
L
L
L
L
L
L
L
L
LCAS
H
H
L
H
L
L
H
L
L
UCAS
H
H
H
L
L
H
L
L
L
WE
H
H
H
H
H
L
L
L
H
OE
H
H
L
L
L
H
H
H
H
I/O1-I/O8
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
I/O9-I/O16
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Operation
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
Pin Names
A0-A8
RAS
UCAS, LCAS
WE
OE
I/O1 – I/O16
Address Inputs
Row Address Strobe
Column Address Strobe
Read/Write Input
Output Enable
Data Input/Output
Power Supply:
+ 5 V for HYB 514265,
+ 3.3 V for HYB 314265
Ground (0 V)
No Connection
V
CC
V
SS
N.C.
Semiconductor Group
2
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Pin Configuration
(top view)
P-SOJ-40-3
Semiconductor Group
3
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Block Diagram
Semiconductor Group
4
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Absolute Maximum Ratings
Operating temperature range ........................................................................................ 0 to + 70
°C
Storage temperature range..................................................................................... – 55 to + 150
°C
Input/output voltage for HYB 514265................................................ – 0.5 to min. (
V
CC
+ 0.5, 7.0) V
Power supply voltage for HYB 514265 ........................................................................... – 1 to + 7 V
Input/output voltage for HYB 314265................................................ – 0.5 to min. (
V
CC
+ 0.5, 4.6) V
Power supply voltage for HYB 314265 ..................................................................... – 0.5 to + 4.6 V
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under
“Absolute
Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics for HYB514265
T
A
= 0 to 70
°C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 % (± 5 % for -400 version) ,
t
T
= 2 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5.0 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current, any input
(0 V <
V
IN
< 7 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V <
V
OUT
<
V
CC
)
Average
V
CC
supply current:
-400 version
-40 version
-45 version
-50 version
Standby
V
CC
supply current
(RAS = LCAS = UCAS = WE =
V
IH
)
Symbol
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
Limit Values
min.
max.
2.4
V
CC
+ 0.5
– 0.5
0.8
2.4
–
–
0.4
– 10
10
– 10
–
120
120
105
95
2
10
Unit Notes
V
V
V
V
µA
µA
1
1
1
1
1
1
mA
2, 3, 4
I
CC2
I
CC3
–
–
mA
–
Average
V
CC
supply current during RAS-only
refresh cycles:
-400 version
-40 version
-45 version
-50 version
120
120
105
95
mA
2, 4
Semiconductor Group
5
京公网安备 11010802033920号
EEWORLD
