SPL11A Programming Guide
V0.1 – Oct. 23, 2002
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PRELIMINARY
SPL11A PROGRAMMING GUIDE
0 Table of Content
0
1
2
TABLE OF CONTENT ..................................................................................................................................... 2
REVISION HISTORY ....................................................................................................................................... 5
INTRODUCTION .............................................................................................................................................. 6
2.1 G
ENERAL
D
ESCRIPTION
............................................................................................................................ 6
2.2 F
EATURE
................................................................................................................................................. 6
2.3 A
PPLICATION
............................................................................................................................................ 7
2.4 S
TRUCTURE
D
IAGRAM
............................................................................................................................... 8
3
MEMORY ......................................................................................................................................................... 9
3.1 M
EMORY
M
APPING
................................................................................................................................... 9
3.2 M
EMORY LOCATION
................................................................................................................................. 10
3.3 V
ECTOR
................................................................................................................................................ 10
3.4 E
RROR
-
ADDRESS AREA
........................................................................................................................... 10
3.5 E
XAMPLE
............................................................................................................................................... 10
4
CPU CLOCK CONTROL ................................................................................................................................11
4.1 C
LOCK
S
OURCE
C
ONTROL
.......................................................................................................................11
4.1.1 Clock sources combination (OTP)..........................................................................................11
4.2 CPU C
LOCK
C
ONTROL
R
EGISTER
............................................................................................................11
4.2.1 P_05H_CPU_CLK ($0005):
set CPU clock
..........................................................................11
5
IO AND RFC FUNCTION ............................................................................................................................... 12
5.1 P
ORT
A(IOA) C
ONTROL
R
EGISTER
........................................................................................................... 12
5.1.1 P_00H_IOA_Data ($0000): Data register of PortA ................................................................ 12
5.1.2 P_01H_IOA_Dir ($0001): Direction Control register of PortA ................................................ 12
5.1.3 P_02H_IOA_Attrib ($0002): Attribute data register of PortA.................................................. 12
5.2 R
ESISTOR TO
F
REQUENCY
C
ONVERTER
(RFC) F
UNCTION
.......................................................................... 14
5.2.1 P_13H_RFC_CTL ($0013):
RFC Control Register
............................................................ 14
5.2.2 How to use RFC function....................................................................................................... 15
5.2.3 Function description of PortA(IOA[7:0])................................................................................. 15
5.2.4 IOA Structure......................................................................................................................... 16
5.3 P
ORT
B(INB) C
ONTROL
R
EGISTER
........................................................................................................... 18
5.3.1 P_03H_INB_Data ($0003)..................................................................................................... 18
Sunplus Technology Co., Ltd.
PAGE 2
V0.1 – OCT. 23, 2002
PRELIMINARY
SPL11A PROGRAMMING GUIDE
5.3.2 P_10H_IO_Config ($0010) .................................................................................................... 18
5.3.3 INB Structure......................................................................................................................... 19
6
SYSTEM CONTROL ...................................................................................................................................... 20
6.1 S
YSTEM
C
ONTROL
.................................................................................................................................. 20
6.1.1 P_0FH_SYS_SWITCH ($000F) ............................................................................................ 20
6.1.2 P_0FH_SYS_SWITCH ($000F) ............................................................................................ 21
6.2 R
ESET
F
LAGS
........................................................................................................................................ 22
6.2.1 P_12H_RST_FG ($0012) ...................................................................................................... 22
7
TIMER/COUNTER ......................................................................................................................................... 23
7.1 T
IMER
S
TRUCTURE
................................................................................................................................. 23
7.2 T
IMER
S
ETUP
& I
NITIALIZATION
................................................................................................................ 23
7.2.1 P_09H_TIMER_SET ($0009): Set the timer/counter configuration ....................................... 23
7.3 T
IMER
/I
NTERRUPT
C
LOCK
S
OURCES
........................................................................................................ 24
A. HSCK sources for timer, interrupt ................................................................................................ 24
7.3.1 P_0CH_TIMER_INT1 ($000C) .............................................................................................. 24
B.
LSCK(32768) sources for timer, interrupt sources ................................................................... 25
7.3.2 P_0DH_TIMER_INT2 ($000D) .............................................................................................. 25
7.4 T
IMER
D
ATA
R
EGISTER
............................................................................................................................ 26
7.4.1 P_0AH_TML_LATCH ($000A)............................................................................................... 26
7.4.2 P_0BH_TMH_LATCH ($000B) .............................................................................................. 26
8
LCD ................................................................................................................................................................ 27
8.1 LCD RAM
MAPPING
............................................................................................................................... 27
8.2 C
ONTROL REGISTERS
.............................................................................................................................. 27
8.2.1 Port_LCD_CTL ($0004)......................................................................................................... 27
8.2.2 LCD clock control .................................................................................................................. 29
8.3 M
ULTIPLE FUNCTIONS
(I/O,
SEGMENT
&
COMMON SHARING
) ....................................................................... 30
8.3.1 LCD dot & I/O ........................................................................................................................ 30
8.3.2 LCD mapping with dot resolution........................................................................................... 31
9
WAKEUP / INTERRUPT ................................................................................................................................ 32
9.1 W
AKEUP
/I
NTERRUPT
S
TRUCTURE
D
IAGRAM
.............................................................................................. 32
9.2 W
AKEUP
/I
NTERRUPT
C
ONTROL REGISTERS
............................................................................................... 33
9.2.1 P_07H_WKU_SET ($0007)................................................................................................... 33
9.2.2 Port_WKU_CLR ($0008) ....................................................................................................... 34
9.2.3 P_0EH_INT_SET($000E)...................................................................................................... 34
Sunplus Technology Co., Ltd.
PAGE 3
V0.1 – OCT. 23, 2002
PRELIMINARY
SPL11A PROGRAMMING GUIDE
10 REMOTE CONTROL ..................................................................................................................................... 36
10.1 R
EMOTE CONTROL MODULE DIAGRAM
........................................................................
錯誤! 尚未定義書籤。
10.2 C
ONTROL REGISTERS
.............................................................................................................................. 36
10.2.1 P_06H_DUTY_CTL ($0006).................................................................................................. 36
11 DEVELOPMENT SYSTEM ............................................................................................................................ 37
11.1 SPL11A S
IMULATOR
.............................................................................................................................. 37
11.2 OTP W
RITER AND DEMO BOARD
.............................................................................................................. 37
12 MASK/BONDING OPTION ............................................................................................................................ 39
12.1 M
ASK OPTIONS FOR
ROM
VERSION OF
SPL11A ....................................................................................... 39
12.2 B
ONDING OPTIONS FOR
OTP
VERSION OF
SPL11A ................................................................................... 39
12.3 D
EFAULT STATUS OF PINS
........................................................................................................................ 39
13 APPENDIX ..................................................................................................................................................... 40
13.1 P
ORT AND
M
EMORY
M
AP
......................................................................................................................... 40
13.2 OTP (QFP) PIN D
ESCRIPTION
............................................................................................................... 41
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PAGE 4
V0.1 – OCT. 23, 2002
PRELIMINARY
SPL11A PROGRAMMING GUIDE
1 Revision History
Revision
Date
By
Remark
Sunplus Technology Co., Ltd.
PAGE 5
V0.1 – OCT. 23, 2002
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